HT48E10 Holtek Semiconductor, HT48E10 Datasheet - Page 13

• Manufacturer Part Number: HT48E10
• Description: I/O Type 8-Bit MTP MCU
• Manufacturer: Holtek Semiconductor

measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it re-
ceives further transient pulse. Note that, in this operat-
ing mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues the interrupt request just like the other two
modes. To enable the counting operation, the timer ON
bit (TON; bit 4 of the TMRC) should be set to 1. In the
pulse width measurement mode, the TON will be
cleared automatically after the measurement cycle is
completed. But in the other two modes the TON can only
be reset by instructions. The overflow of the timer/event
counter is one of the wake-up sources. No matter what
the operation mode is, writing a 0 to ETI can disable
the corresponding interrupt services.
Rev. 1.50
Bit No.
0~2
3
4
5
6
7
PSC0~PSC2
Label
TON
TM0
TM1
TE
Defines the prescaler stages, PSC2, PSC1, PSC0=
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: f
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable or disable timer 0 counting (0=disable; 1=enable)
Unused bit, read as 0
Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
INT
INT
INT
INT
INT
INT
INT
INT
=f
=f
=f
=f
=f
=f
=f
=f
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
/2
/4
/8
/16
/32
/64
/128
/256
TMRC (0EH) Register
Timer/Event Counter
13
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register will also
reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until overflow
occurs. When the timer/event counter (reading TMR) is
read, the clock will be blocked to avoid errors. As clock
blocking may result in a counting error, this must be
taken into consideration by the programmer.
Bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of the
timer/event counter. The definitions are as shown. The
overflow signal of the timer/event counter can be used
to generate PFD signals for buzzer driving.
Function
October 31, 2006
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HT48E10