HT48E10 Holtek Semiconductor, HT48E10 Datasheet - Page 19

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HT48E10

Manufacturer Part Number
HT48E10
Description
I/O Type 8-Bit MTP MCU
Manufacturer
Holtek Semiconductor
Datasheet
ERAL
The ERAL instruction erases the entire 128 8 memory
cells to a logical 1 state in the programming enable
mode. After the erase-all instruction set has been is-
sued, the data erase feature is activated by the falling
edge of CS. Since the internal auto-timing generator
provides all timing signal for the erase-all operation, so
the SK clock is not required. During the internal erase-all
operation, the busy/ready status can be verified if CS is
high. The DO will remain low but when the operation is
over, the DO will return to high and further instruction
can be executed.
EECR Control Timing Diagrams
Rev. 1.50
READ
EWEN/EWDS
WRITE
19
WRAL
The WRAL instruction writes data into the entire 128 8
memory cells in the programming enable mode. After the
write-all instruction set has been issued, the data writing
is activated by the falling edge of CS. Since the internal
auto-timing generator provides all timing signals for the
write-all operation, so the SK clock is not required. During
the internal write-all operation, the busy/ready status can
be verified if CS is high. The DO will remain low but when
the operation is over the DO will return to high and further
instruction can be executed.
October 31, 2006
www.DataSheet4U.com
HT48E10

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