HT48E10 Holtek Semiconductor, HT48E10 Datasheet - Page 11

• Manufacturer Part Number: HT48E10
• Description: I/O Type 8-Bit MTP MCU
• Manufacturer: Holtek Semiconductor

The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by options. Awakening from an I/O port stimulus,
the program will resume execution of the next instruc-
tion. If it awakens from an interrupt, two sequence may
occur. If the related interrupt is disabled or the interrupt
is enabled but the stack is full, the program will resume
execution at the next instruction. If the interrupt is en-
abled and the stack is not full, a regular interrupt re-
sponse takes place. If an interrupt request flag is set to
tion of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 (system clock pe-
riod) to resume to normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
The time-out during HALT is different from other chip re-
set conditions, since it can perform a warm reset that
resets only the Program Counter and Stack Pointer,
leaving the other circuits in their original state. Some
registers remain unchanged during other reset condi-
tions. Most registers are reset to the initial condition
when the reset conditions are met. By examining the
PDF and TO flags, the program can distinguish between
different chip resets .
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the sys-
tem resets (power-up, WDT time-out or RES reset) or
the system awakes from the HALT state.
Rev. 1.50
1 before entering the HALT mode, the wake-up func-
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
TO
0
u
0
1
1
PDF
0
u
1
u
1
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
WDT time-out during normal operation
WDT wake-up HALT
RESET Conditions
11
Note:
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able an SST delay.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The functional unit chip reset status are shown below.
Program Counter
Interrupt
Prescaler
WDT
Timer/Event Counter
Input/Output Ports
Stack Pointer
nected to the RES pin as short as possible, to
avoid noise interference.
* Make the length of the wiring, which is con-
Reset Configuration
Reset Timing Chart
Reset Circuit
000H
Disable
Clear
Clear. After master reset,
WDT begins counting
Off
Input mode
Points to the top of the stack
October 31, 2006
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HT48E10