LM3S101 Luminary Micro, Inc., LM3S101 Datasheet - Page 201

• Manufacturer Part Number: LM3S101
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

October 5, 2006
Reset
Reset
Type
Type
Bit/Field
31:8
UART Flag (UARTFR)
Offset 0x018
7
6
5
RO
RO
31
15
0
0
Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
RO
RO
30
14
0
0
reserved
Name
TXFE
RXFF
TXFF
RO
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
0
1
0
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
UART Transmit FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled (FEN is 0), this bit is set when the transmit
holding register is empty.
If the FIFO is enabled (FEN is 1), this bit is set when the transmit
FIFO is empty.
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding
register is full.
If the FIFO is enabled, this bit is set when the receive FIFO is
full.
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding
register is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is
full.
RO
RO
24
0
0
8
reserved
TXFE
RO
RO
23
0
7
1
RXFF
RO
RO
22
0
6
0
TXFF
RO
RO
21
0
5
0
RXFE
RO
RO
20
0
4
1
BUSY
RO
RO
19
0
3
0
LM3S101 Data Sheet
RO
RO
18
0
0
2
reserved
RO
RO
17
0
0
1
RO
RO
16
0
0
0
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