LM3S315 Luminary Micro, Inc., LM3S315 Datasheet - Page 104

• Manufacturer Part Number: LM3S315
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Internal Memory
104
Reset
Reset
Type
Type
Bit/Field
31:30
Flash Memory Protection Read Enable (FMPRE)
Offset 0x130 and 0x134
29:8
7:0
R/W0
RO
31
15
1
0
DBG
Register 1: Flash Memory Protection Read Enable (FMPRE), offset 0x130
Note:
This register stores the read-only (FMPRE) protection bits for each 2-KB flash block and bits to
disable debug access through JTAG and SWD. This register is loaded during the power-on reset
sequence.
The factory setting for the FMPRE register is a value of 1 for all implemented flash banks and 0x2
for the DBG field. These bits implement a policy of open access, programmability, and debug
access. The register bits may be changed by writing the specific register bit. However, this register
is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a
1).
The changes are not permanent until the register is committed (saved), at which point the bit
change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by
executing a power-on reset sequence.
For additional information, see “Flash Memory Protection” on page 87.
R/W0
RO
30
14
0
0
reserved
Block7-
Block0
Name
DBG
RO
RO
29
13
Offset is relative to System Control base address of 0x400FE000
0
0
RO
RO
28
12
0
0
reserved
RO
RO
R/W0
R/W0
27
11
Type
0
0
RO
RO
RO
26
10
0
0
RO
RO
25
0
9
0
Preliminary
Reset
0xFF
0x2
0
RO
RO
24
0
8
0
reserved
Block7
R/W0
RO
23
0
7
1
Description
Controls access to the debug access port (DAP)
through the JTAG and SWD interfaces. A value of
0x2 enables access. A value of 0 disables access.
Reserved bits return an indeterminate value, and
should never be changed.
Enable 2-KB flash blocks to be executed or read.
The policies may be combined as shown in Table
Table 7-1 on page 100.
Block6
R/W0
RO
22
0
6
1
Block5
R/W0
RO
21
0
5
1
Block4
R/W0
RO
20
0
4
1
Block3
R/W0
RO
0
19
3
1
Block2
R/W0
RO
0
18
2
1
Block1
April 27, 2007
R/W0
RO
0
17
1
1
Block0
R/W0
RO
0
16
0
1