LM3S315 Luminary Micro, Inc., LM3S315 Datasheet - Page 35

• Manufacturer Part Number: LM3S315
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
April 27, 2007
Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris devices. This means Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris devices have implemented TPIU as shown in Figure 2-2. This is
similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual,
however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S315 controller and supports the
standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full
support for protection regions, overlapping protection regions, access permissions, and exporting
memory attributes to the system.
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of
priority. The NVIC and the processor core interface are closely coupled, which enables low latency
Facilitates low-latency exception and interrupt handling
Controls power management
Implements system control registers
Debug
Slave
Slave
ATB
APB
Port
Port
Interface
Interface
ATB
APB
Preliminary
Asynchronous FIFO
(serializer)
Trace Out
LM3S315 Data Sheet
Serial Wire
Trace Port
(SWO)
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