LM3S328-IQN25(T) Luminary Micro, Inc., LM3S328-IQN25(T) Datasheet - Page 297
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LM3S328-IQN25(T)
Manufacturer Part Number
LM3S328-IQN25(T)
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S328-IQN25T.pdf
(359 pages)
- Current page: 297 of 359
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14
14.1
14.2
October 8, 2006
Inter-Integrated Circuit (I
The Inter-Integrated Circuit (I
design (a serial data line SDL and a serial clock line SCL).
The I
networking devices, LCDs, tone generators, and so on. The I
testing and diagnostic purposes in product development and manufacture.
The Stellaris I
The I
Devices on the I
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I
Receive, Slave Transmit, and Slave Receive.
The Stellaris I
Both the I
a transmit or receive operation completes (or aborts due to an error). The I
interrupts when data has been sent or requested by a master.
Block Diagram
Figure 14-1. I
Functional Description
The I
are implemented as separate peripherals. The I
Open-Drain pads. A typical I
See “I2C Timing” on page 345 for I
Interrupt
2
2
2
C module is comprised of both a master and slave function. The master and slave functions
C bus interfaces to external I
C bus supports devices that can both transmit and receive (write and read) data.
2
C master and slave can generate interrupts. The I
I2CMTPR
I2CMIMR
I2CMMIS
I2CMICR
I2CMRIS
I2CMSA
I2CMCS
I2CMDR
I2CMCR
2
2
C module provides the ability to communicate to other IC devices over an I
C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
2
2
C Block Diagram
C bus can be designated as either a master or a slave. The I
I
2
C Control
I2CSOAR
I2CSCSR
2
I2CSMIS
I2CSICR
I2CSRIS
I2CSDR
2
I2CSIM
C bus configuration is shown in Figure 14-2.
C) bus provides bi-directional data transfer through a two-wire
2
2
Preliminary
C timing diagrams.
C devices such as serial memory (RAMs and ROMs),
2
2
I
C module must be connected to bi-directional
2
I
2
C) Interface
C Master Core
C Slave Core
2
C modes are: Master Transmit, Master
2
2
C master generates interrupts when
C bus may also be used for system
I2CSCL
I2CSDA
I2CSCL
I2CSDA
2
C slave generates
I
2
C I/O Select
2
LM3S328 Data Sheet
C module supports
2
I2CSCL
I2CSDA
C bus.
297
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