LM3S328-IQN25(T) Luminary Micro, Inc., LM3S328-IQN25(T) Datasheet - Page 320
![no-image](/images/no-image-200.jpg)
LM3S328-IQN25(T)
Manufacturer Part Number
LM3S328-IQN25(T)
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S328-IQN25T.pdf
(359 pages)
- Current page: 320 of 359
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Inter-Integrated Circuit (I2C) Interface
320
Reset
Reset
Type
Type
Bit/Field
I2C Master Configuration (I2CMCR)
Offset 0x020
31:6
3:1
5
4
0
RO
RO
31
15
0
0
Register 9: I
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
RO
RO
30
14
0
0
reserved
reserved
Name
LPBK
RO
RO
MFE
SFE
29
13
0
0
2
RO
RO
C Master Configuration (I2CMCR), offset 0x020
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
R/W
R/W
reserved
RO
RO
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
I
This bit specifies whether the interface may operate in
Slave mode. If set, Slave mode is enabled; otherwise,
Slave mode is disabled.
I
This bit specifies whether the interface may operate in
Master mode. If set, Master mode is enabled; otherwise,
Master mode is disabled and the interface clock is disabled.
Reserved bits return an indeterminate value, and should
never be changed.
I
This bit specifies whether the interface is operating
normally or in Loopback mode. If set, the device is put in a
test mode loopback configuration; otherwise, the device
operates normally.
2
2
2
C Slave Function Enable
C Master Function Enable
C Loopback
RO
RO
23
0
7
0
RO
RO
22
0
6
0
SFE
R/W
RO
21
0
5
0
MFE
R/W
RO
20
0
4
0
RO
RO
19
0
3
0
reserved
RO
RO
18
0
2
0
October 8, 2006
RO
RO
17
0
1
0
LPBK
R/W
RO
16
0
0
0
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