UPD77016 NEC, UPD77016 Datasheet
UPD77016
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UPD77016 Summary of contents
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Fixed-point Digital Signal Processor PD77016 bits fixed-point DSP (Digital Signal Processor) developed for digital signal processing with its demand for high speed and precision. FEATURES FUNCTIONS • Instruction cycle (MIN.) with 33 MHz ...
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External Memory X Memory Serial Data I/O #1 Pointers Serial I/O #2 Ports Interrupt Control Host I/O Wait Controller INT1–INT4 IE I/O X–Bus Y–Bus X Memory Y Memory Y Memory 2KW–RAM Data 2KW–RAM Pointers Main Bus Loop Instruction Control Memory ...
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FUNCTIONAL PIN GROUPS SO1 SORQ1 SOEN1 Serial SCK1 Interface #1 SI1 SIEN1 SIAK1 SO2 SORQ2 SOEN2 Serial SCK2 Interface #2 SI2 SIEN2 SIAK2 Ports (4) HCS HA0,HA1 (2) HRD Host Interface HRE HWR HWE HD0 - HD7 ...
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... MHz) 33/16.5/8.25/4.125 MHz Variable multiple rate ( mask option. 33 MHz STOP instruction is added. Channel 1 has the same functions as that of the PD77016. Channel 2 has no SORQ2 or SIAK2 pin (Channel 2 is used for CODEC connection). 100-pin plastic TQFP PD77018A PD77019 PD77019-013 4K words ...
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PIN CONFIGURATION PD77016GM-KMD 160-pin plastic QFP (FINE PITCH) (24 160 159 158 157 156 155 154 153 152 151 RESET 1 INT4 2 INT3 3 INT2 4 INT1 5 WAIT 6 HOLDRQ 7 CLKIN ...
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... Host Write IA0-IA15: Instruction Memory Address Output ID0-ID31: Instruction Data Input INT1-INT4: Interrupt MRD: Memory Read Output MWR: Memory Write Output N.C: No Connection P0-P3: Port PWR: Program Memory Write Strobe RESET: Reset SCK1,SCK2: Serial Clock Input SI1,SI2: Serial Data Input SIAK1,SIAK2: Serial Input Acknowledge ...
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Pin No. Symbol Pin No. 1 RESET 41 D15 2 INT4 42 D14 3 INT3 43 D13 4 INT2 44 D12 5 INT1 45 GND 6 WAIT HOLDRQ 47 D11 8 CLKIN 48 D10 9 P3 ...
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... PIN FUNCTIONS ............................................................................................................................... 1.1 Pin Functions ........................................................................................................................................... 1.2 Recommended Connection for Unused Pins ....................................................................................... 14 2. FUNCTIONS ...................................................................................................................................... 15 2.1 Pipeline Processing ................................................................................................................................ 15 2.1.1 Outline ........................................................................................................................................... 15 2.1.2 Instructions with Delay .................................................................................................................. 15 2.2 Program Control Unit .............................................................................................................................. 16 2.3 Operation Unit ......................................................................................................................................... 16 2.3.1 General register (R0 to R7) ........................................................................................................... 16 2.3.2 MAC: Multiply ACcumulator ......................................................................................................... 17 2.3.3 ALU: Arithmetic Logic Unit ........................................................................................................... 17 2.3.4 BSFT: Barrel ShiFTer ................................................................................................................... 17 2.3.5 SAC: Shifter And Count Circuit .................................................................................................... 17 2 ...
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PIN FUNCTIONS 1.1 Pin Functions • Power supply Symbol Pin No. V 15, 26, 36, 46, 56, 62, 71, DD 95, 106, 116, 131, 141, 151 GND 14, 25, 35, 45, 55, 61, 70, 94, 105, 115, 130, 140, ...
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External data memory interface Symbol Pin No. X/Y 20 DA15 - DA0 Note 1. D15 - D0 Note 2. MRD 17 MWR 16 WAIT 6 HOLDRQ 7 BSTB 18 HOLDAK 19 Note 1. DA15 to DA0 pins are located ...
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Serial interface Symbol Pin No. SCK1 65 SORQ1 68 SOEN1 69 SO1 67 SIEN1 64 SI1 63 SCK2 76 SORQ2 73 SOEN2 72 SO2 74 SIEN2 77 SI2 78 SIAK1 66 SIAK2 75 Remark The state of the pins ...
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Host interface Symbol Pin No. HA1 83 HA0 82 HCS 79 HRD 80 HWR 81 HRE 92 HWE 93 HD7 - HD0 Remark The state of the pins added 3S becomes high impedance when the host ...
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External instructions memory interface Symbol Pin No. IA15 - IA0 Note 1. ID31 - ID0 Note 2. PWR 129 Note 1. IA15 to IA0 pins are located on these pins: 101 to 104, 107 to 114, 117 to 120 ...
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... But in the HALT mode when the current consumption is reduced, connect a pin as recommended connection. 2. Can leave open, if HCS, HRD, HWR are fixed to high level. But in the HALT mode when the current consumption is reduced, connect a pin as recommended connection. Remark I: Input pin, O: Output pin, I/O: Input/Output pin 14 ...
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FUNCTIONS 2.1 Pipeline Processing This section describes the PD77016 pipeline processing. 2.1.1 Outline The PD77016 basic operations are executed in following 3-stage pipeline. (1) instruction fetch; if (2) Instruction decoding; id (3) execution; ex When the PD77016 operates a ...
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Program Control Unit Program control unit controls not only count up of program counter in normal operation, but loop, repeat, branch, halt and interrupt. In addition to loop stack of loop 4 level and program stack of 15 level, ...
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General register used as 24 bits register Bit 39 to bit 16 of general register are treated as 24 bits register, when it is used for destination with extended sign for a load/store instruction. (4) General register used as ...
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Memory The PD77016 has one instruction memory area (64K words 32 bits) and two data memory areas (64K words 16 bits each). It adopts Harvard-type architecture, with instruction memory area and data memory areas separated. The PD77016 has 2 ...
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Instruction RAM Outline The PD77016 has an instruction RAM (1.5 words of the instruction RAM. Internal RAM is initialized and rewritten by boot program. Additionally external memory expansion is available as the instruction memory. When RAM is used as ...
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On-chip Peripheral Circuit The PD77016 includes serial interface, host interface, general input/output ports and wait cycle registers. They are mapped in both X and Y memory areas, and are accessed as memory mapped I/O by the PD77016 CPU. 2.5.1 ...
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INSTRUCTIONS 3.1 Outline All PD77016 instructions are one-word instructions, consisting of 32 bits. And they are executed (min.) per instruction. There are following 9 instruction types. (1) Trinomial instructions : specify the Acc operation ...
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Instruction Set and Operation An operation is written according to the rules for expressing. An expression of instructions having two or more descriptions can have only one selected. (a) Expressions and selectable registers Expression and selectable registers are shown ...
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Modifying data pointers Data pointers are modified after memory access. The results are valid immediately after instruction execution impossible to modify without memory access. Description DPn No operation: DPn value does not change. DPn++ DPn DPn+1 DPn– ...
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PD77016 INSTRUCTION SET Name Mnemonic Multiply add rh' Multiply sub ro = ro–rh rh' Sign unsign Multiply add (rl should be a plus integral number.) Trinomial Unsign unsign ro=ro+rl ...
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Name Mnemonic And ro" & ro' Immediate and ro & imm Or ro" ro' Immediate or ro imm Dyadic Exclusive or ro" ro' Immediate exclusive or ro ...
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Name Mnemonic Cumulation ro Degression ro'– Division ro Monadic Parallel load/store ro= dpx_mod ro'= dpy_mod Note1, Note2. ro= dpx_mod dpy_mod=rh dpx_mod=rh ro= dpy_mod dpx_mod=rh dpy_mod=rh' Load/store Section load/store dest= dpx_mod dest'= dpy_mod Note1, Note2, ...
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Name Mnemonic Direct addressing dest = addr load/store Note 1. addr = source Load/store Immediate index dest = dp_imm load/store Note 2. dp_imm = source Inter-register transfer dest = rl Inter-register Note 3. transfer rl = source Immediate data set ...
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Name Mnemonic Jump JMP imm Inter-register indirect jump JMP dp Subroutine call CALL imm Inter-register indirect CALL dp Branch subroutine call Return RET Return from interrupt RETI Repeat REP count Loop LOOP count Hardware (Mnemonics more than two lines) loop ...
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ELECTRICAL SPECIFICATIONS Absolute maximum ratings (T = +25 ˚C) A Parameters Power supply voltage Input voltage Output voltage Storage temperature Operating ambient temperature Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings ...
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Measurement Standards Common to Switching Characteristics 0 CLKIN 0 0 2.2 V Input 1.5 V (except for CLKIN) 0.8 V 2.2 V Output 1 Characteristics (T = –40 to +85 ...
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Reset, Interrupt Required Timing Condition Parameters Symbol RESET low level width t w(RL) RESET recovery time t rec(R) INT1-INT4 low level width t w(INTL) INT1-INT4 recovery time t rec(INT) Clock Input/Output Timing t cCI t t wCIH wCIL CLKIN t ...
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External Data Memory Access Required Timing Condition Parameters Read data setup time Read data hold time WAIT setup time WAIT hold time Switching Characteristics Parameters Address output delay time MRD output delay time MRD hold time Write data setup time ...
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External Data Memory Read Operation CLKOUT t dDA DA0 - DA15, X D15 t dDR MRD t suWA WAIT External Data Memory Write Operation CLKOUT t dDA DA0 - DA15, X/Y Hi D15 t dDW MWR ...
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External Instruction Memory Access Required Timing Condition Parameters ID setup time (to CLKOUT ) ID hold time (to CLKOUT ) Switching Characteristics Parameters IA output delay time IA hold time ID write setup time ID write hold time PWR output ...
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External Instruction Memory Read Operation CLKOUT Hi-Z IA0 - IA15 ID0 - ID31 Hi-Z PWR RESET External Instruction Memory Write Operation CLKOUT IA0 - IA15 ID0 - ID31 PWR t hIA t dIA t dIW t hIA t sIDW Hi-Z ...
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Bus Arbitration Required Timing Condition Parameters HOLDRQ setup time HOLDRQ hold time Switching Characteristics Parameters BSTB hold time BSTB output delay time HOLDAK output delay time HOLDAK hold time Data hold time when bus arbitration Data valid time after bus ...
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Bus Arbitration Timing (Bus idle) CLKOUT (Bus busy) t hBS BSTB t suHRQ HOLDRQ HOLDAK X/Y, DA0 - DA15, MRD, MWR Bus idle Bus release t dBS t hHRQ t dHAK t h(BS-D) Bus idle (Bus busy suHRQ ...
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Bus Arbitration Timing (Bus busy) CLKOUT (Bus busy) BSTB t suHRQ HOLDRQ HOLDAK X/Y, DA0 - DA15, MRD, MWR Bus busy Bus idle Bus release t t hBS dBS t hHRQ t dHAK t h(BS-D) Bus idle (Bus busy) t ...
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Bus Arbitration Timing (Bus slave) CLKOUT Load/store External Memory Bus idle BSTB HOLDRQ X/Y, DA0 - DA15, Hi-Z MRD, MWR HOLDAK Bus hold Bus idle Hi-Z ...
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Serial Interface Required Timing Condition Parameters SCK input cycle time SCK input high/low level width SCK input rise/fall time SOEN recovery time SOEN hold time SIEN recovery time SIEN hold time SI setup time SI hold time Switching Characteristics Parameters ...
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Serial Output Timing 1 t cSC t t wSC wSC SCK1, SCK2 t dSOR SORQ1, SORQ2 t recSOE t hSOE SOEN1, SOEN2 SO1, Hi-Z SO2 t hSOR t recSOE t hSOE t t vSO vSO 1st t t rfSC rfSC ...
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Serial Output Timing 2 (Continual output) t cSC t t wSC wSC SCK1, SCK2 t dSOR SORQ1, SORQ2 SOEN1, SOEN2 SO1, SO2 t hSOR t recSOE t hSOE t vSO Last 1st t t rfSC rfSC Hi-Z Last ...
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Serial Input Timing 1 t cSC t t wSC wSC SCK1, SCK2 t dSIA SIAK1, SIAK2 t recSIE t hSIE SIEN1, SIEN2 SI1, SI2 t hSIA t recSIE t hSIE t t suSI hSI 1st t t rfSC rfSC 3rd ...
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Serial Input Timing 2 (Continual input) t cSC t t wSC wSC SCK1, SCK2 t dSIA SIAK1, SIAK2 SIEN1, SIEN2 SI1, Last–1 SI2 t hSIA t recSIE t hSIE t t suSI hSI Last 1st t t rfSC rfSC 2nd ...
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Host Interface Required Timing Condition Parameters HRD delay time HRD width HCS, HA0, HA1 read hold time HCS, HA0, HA1 write hold time HRD, HWR recovery time HWR delay time HWR width HWR hold time HWR setup time Switching Characteristics ...
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Host Read Interface Timing CLKOUT HCS, HA0, HA1 t dHR HRD Hi-Z HD0 - HD7 t dHE HRE t hHCAR t t wHR recHS t hHDR t vHDR Hi-Z t hHE ...
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Host Write Interface Timing CLKOUT HCS, HA0, HA1 t dHW HWR HD0 - HD7 t dHE HWE t hHCAW t t wHW recHS t hHDW t suHDW t hHE ...
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General Input/Output Ports Required Timing Condition Parameters Port input setup time Port input hold time Switching Characteristics Parameters Port output delay time General Input/Output Ports Timing CLKOUT (Output (Input) 48 Symbol Conditions MIN. t ...
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Debugging Interface (JTAG) Required Timing Condition Parameters TCK cycle time TCK high level width TCK low level width TCK rise/fall time TMS, TDI setup time TMS, TDI hold time Input pin setup time Input pin hold time Switching Characteristics Parameters ...
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PACKAGE DRAWING 160 PIN PLASTIC QFP (FINE PITCH) ( 120 121 160 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. 50 24) A ...
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RECOMMENDED SOLDERING CONDITIONS When soldering this product highly recommended to observe the conditions as shown below. If other soldering processes are used the soldering is performed under different conditions, please make sure to consult with ...
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... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices ...
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... Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...