UPD77019-013 NEC, UPD77019-013 Datasheet - Page 17

• Manufacturer Part Number: UPD77019-013
• Description: 16 bits/ Fixed-point Digital Signal Processor
• Manufacturer: NEC

2.2 Program Control Unit
branch, halt and interrupt.
loop and multi-interrupt/subroutine call.
interrupt enable or disable independently.
input or hardware reset input. It takes several system clock to recover.
reset input. It takes a few ms to recover.
2.3 Operation Unit
of 16 bits
2.3.1 General register (R0 to R7)
register consists of the following three parts.
Program control unit controls not only count up of program counter in normal operation, but loop, repeat,
In addition to loop stack of loop 4 level and program stack of 15 level, software stack can be used for multi-
The PD77019-013 has external 4 interruptions and internal 6 interruptions from peripheral, and specifies
The HALT and STOP instructions cause the PD77019-013 to place in low power standby mode.
When the HALT instruction is executed, power consumption decreases. HALT mode is released by interrupt
When the STOP instruction is executed, power consumption decreases. STOP mode is released by hardware
Operation unit consists of the following five parts.
– 40 bits general register
– 16 bits
– 40 bits Data ALU
– 40 bits barrel shifter
– SAC: shifter and count circuit.
Standard word length is 40 bits to make overflow check and adjustment easy, and to accumulate the result
The PD77019-013 has eight 40 bits registers for operation input/output and load/store with memory. General
– R0L to R7L (bit 15 to bit 0)
– R0H to R7H (bit 31 to bit 16)
– R0E to R7E (bit 39 to bit 32)
But each of RnL, RnH and RnE are treated as a register in the following conditions.
(1) General register used as 40 bits register
General registers are treated as 40 bits register, when they are used for the following aims.
(a) Operand for triminal operation (except for multiplier input)
(b) Operand for dyadic operation (except for multiplier and shift value)
(c) Operand for monadic operation (except for exponent instructions)
(d) Operand for operation
(e) Operand for conditional judge
(f) Destination for load instruction (with sign extension and 0 clear)
16 bits multiplication correctly.
16 bits + 40 bits
39
S S S S S S S S
Head room
32
31
8 for data load/store and input/output of operation data
40 bits multiply accumulator
Result of multiplication among two's complement data
Preliminary Data Sheet
PD77019-013
1
0
0
17