AN1740 Freescale Semiconductor / Motorola, AN1740 Datasheet - Page 21

• Manufacturer Part Number: AN1740
• Description: Applications Using the Analog Subsystem on MC68HC05JJ/JP Series Microcontrollers
• Manufacturer: Freescale Semiconductor / Motorola

Comparator
Speed
Comparator
Power
Consumption
Comparator
Output Sampling
AN1740
MOTOROLA
The comparators have good speed and can power up or respond to their
inputs changing within 2 microseconds. However, powering up a
comparator when neither comparator nor the current source was
previously active can result in a longer delay in stabilization for both the
analog bias source and the comparator. It is, therefore, recommended
that at least 10 microseconds of delay be provided by the software to
allow the comparator to stabilize following a power up before trying to
read or reset its output flag bits. The simplest way to add a time delay
would be a series of NOP instructions (at f
takes 1 microsecond) or to insert other code which does not rely on the
state of the comparator output flags.
Each comparator typically draws 100 A of I
powered up by its appropriate CP1EN or CP2EN bit in the ACR. In
addition, when either or both comparators are powered up, an analog
bias source is also powered up which draws typically 65 A. This means
that a single comparator will draw about 165 A and both comparators
will draw about 265 A.
There are two means to determine if a comparator has changed states:
The static flags are set whenever there is a rising edge on the output of
the respective comparator, and they remain latched until cleared by
writing a logical 1 to the respective CPFR1 and CPFR2 bits or by a reset
of the device. These flags are useful for capturing events while the CPU
is doing some other task. These flags also can generate an interrupt
using the analog interrupt. In the case of comparator 2, a timer input
capture interrupt also can be generated. As mentioned above, the state
of the CPF1 and CPF2 flag bits should be ignored after changing the
state of the INV bit until both flags have been reset using the CPFR1 and
CPFR2 reset bits.
The dynamic output bits merely follow the state of the output of each
comparator. There is no timing synchronization in passing the state of
the CMP1 and CMP2 bits to the ASR. The dynamic output bits are useful
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
The static flags, CPF1 and CPF2
The dynamic outputs, CMP1 and CMP2
Go to: www.freescale.com
OSC
DD
of 4.2 MHz, each NOP
current when it is
Voltage Comparators
Application Note
21