AN1740 Freescale Semiconductor / Motorola, AN1740 Datasheet - Page 37

• Manufacturer Part Number: AN1740
• Description: Applications Using the Analog Subsystem on MC68HC05JJ/JP Series Microcontrollers
• Manufacturer: Freescale Semiconductor / Motorola

Sample and Hold
AN1740
MOTOROLA
NOTE:
To cancel the impedance of the channel multiplexers, an identical
dummy multiplexer is switched in at the bottom whenever the DHOLD bit
is set. If more than one channel multiplexer is turned on at the same
time, there will be a shift in the divider ratio due to the parallel
combination of the input multiplexers not being matched by the
compensation multiplexer at the bottom of the divider. A second-order
temperature-dependent term also will be present if the multiplexer
impedance at the top is not equal to the dummy multiplexer at the
bottom. Typical input impedance of both the direct and divided inputs is
given previously in
The divided input is only compensated for one channel multiplexer at a
time. If multiple channel multiplexers are on simultaneously, then the
divider ratio will increase slightly.
The sample capacitor is always connected from the negative input of
comparator 2 to V
between different devices. The capacitor can be charged within 99.9%
of its final value within seven RC time constants.
When connected directly to the channel select bus, the worst case series
impedance of the channel and the HOLD multiplexers is about 8 k for
an RC time of 104 nanoseconds. By comparison, it takes the software
four CPU bus cycles to set and then turn off the HOLD bit. At the
maximum oscillator frequency of 4.2 MHz, this is about a 2-microsecond
delay or about 18 RC time constants. Therefore, if connected directly to
the channel bus, there should always be sufficient time to charge the
sample capacitor between any two instructions.
However, when connected through the divider to the channel bus, the
series impedance of the channel and the DHOLD multiplexers is added
to the 60-k equivalent resistance of the divider. This increases the RC
time constant to a worst case of 832 nanoseconds. With the same 2-
microsecond software delay, this would give a little more than two RC
time constants, which would allow only the sample capacitor to charge
to about 85% of its final value. Therefore, if connected through the
divider to the channel select bus, there should always be sufficient time
to charge the sample capacitor (seven RC time constants or about six
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SS
Figure
. It is typically 10 pF, but can vary from 8 to 13 pF
9.
Support Circuitry
Application Note
37