AN1740 Freescale Semiconductor / Motorola, AN1740 Datasheet - Page 65
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AN1740
Manufacturer Part Number
AN1740
Description
Applications Using the Analog Subsystem on MC68HC05JJ/JP Series Microcontrollers
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
1.AN1740.pdf
(80 pages)
- Current page: 65 of 80
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Automated A/D Conversions
AN1740
MOTOROLA
Mode 2 and mode 3 conversions are mostly under the control of the 16-
bit timer, but they need occasional maintenance to keep flags cleared
and to transfer input capture times to RAM for use by other routines. Due
to the more accurate start and stop timing and high possible bit counts,
mode 2 or mode 3 conversions are best for long conversions of more
than eight bits.
Mode 2 or mode 3 conversions use the timer overflow flag (TOF) or the
output compare flag (OCF) and the input capture flag (ICF) of the 16-bit
timer to control the charging of the integration capacitor connected to
PB0. When using these timer flags, the designer should be aware of
these behaviors:
1. The TOF flag bit is set whenever the 16-bit timer counter overflows
2. The OCF flag bit is set whenever the 16-bit timer counter matches
3. The ICF flag bit is set whenever an input capture is received by the
Freescale Semiconductor, Inc.
For More Information On This Product,
from $FFFF to $0000 regardless of whether or not the timer
overflow interrupt is enabled (TOIE bit set in TCR).
a. Once set, the TOF bit must be reset by the proper software
b. Since the timer starts with $FFFC, a TOF will occur almost
the count stored into the output compare registers regardless of
whether or not the timer output compare interrupt is enabled
(OCIE bit set in TCR).
a. Once set, the OCF bit must be reset by the proper software
b. Once set, the OCF will lock out any future compares until the
c. An OCF can occur at any time after a reset, since the contents
16-bit timer regardless of whether or not the timer input capture
interrupt is enabled (ICIE bit set in TCR).
sequence of reading the TSR, then the TMRL.
immediately after a reset.
sequence of reading the TSR, then the OCRL.
OCF flag bit is cleared.
of the OCRL and OCRH are unaffected by a reset.
Go to: www.freescale.com
Automated A/D Conversions
Application Note
65
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