AN1934 Freescale Semiconductor / Motorola, AN1934 Datasheet

AN1934

Manufacturer Part Number

AN1934

Description

Effects of Skew and Jitter on Clock Tree Design

Manufacturer

Freescale Semiconductor / Motorola

Datasheet

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Effects of Skew and Jitter on

Clock Tree Design

Prepared by: Don Aldridge and Tom Borr

September, 2001

ABSTRACT

jitter as these terms apply to PLL clock drivers and clock

buffers. The application note covers the definition of the various

types of skew and jitter, the measurement techniques and

values associated with these parameters, and concludes with

an example clock tree design and analysis of the skew and

jitter.

INTRODUCTION

As shown in Figure 1, a typical clock distribution tree consists

of a clock source and a series of clock distribution buffers that

deliver multiple copies of the clock source to many locations in

an electronic system. The clock source may be a crystal

oscillator (Figure 1) or an external clock source. This clock

source may be at the desired frequency or may need to be

translated to the desired frequency or frequencies as part of the

clock tree circuitry. The clock tree will consist of some

combination of PLL clock drivers and/or fanout buffers

providing multiple outputs. The clock tree may consist of

several devices or be composed of a single integrated circuit.

Individual clock outputs deliver the clock signal to various

locations on a PC board.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

This application note discusses the parametrics of skew and

At first glance, clock distribution trees are relatively simple.



Motorola, Inc. 2001

Figure 1. Typical Clock Distribution Tree

MPC942C

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Figure 2. Fanout Buffer

system and the data sheet specifications of the devices used

to implement the clock tree, the design appears a bit more

complicated and requires a more detailed analysis. The

specifications that are most important for this type of analysis

are usually found in the AC parameter portion of the clock driver

data sheet and consist of parameters such as propagation

delay, skew, and jitter.

reviewing the definition, the measurement techniques, and

their effects on system performance. The application note

concludes with the analysis of a typical clock distribution tree

based upon these parameters.

Standards for Skew, Jitter Definitions, and Notations

jitter definitions, and notations for this application note are the

EIA specification EIA/JESD65. This EIA specification

documents the current industry standard for these parameters.

This document is available in a downloadable PDF format at the

web site of

Clock Driver Devices

PLL based clock generators. Typical fanout buffers are shown

in Figure 2 and consist of an input buffer driving many outputs

though individual output buffers. The specific devices shown

are the MPC942C and MPC942P which offer 18 LVCMOS

outputs and have either a LVCMOS input or a LVPECL input.

Some fanout buffers have an optional internal divider network

to produce an input clock divided by two. A Phase Lock Loop

device is shown in Figure 4 and may or may not have built–in

fanout buffers. It is not the intention of this application note to

explain all of the fundamentals of a PLL; however, a quick

review of the components is covered.

After a more detailed look at the requirements of the clock

This application note discusses these parameters by

The reference used to determine the standards for skew,

Clock driver devices consist of both clock fanout buffers and

http://www.jedec.org/.

MPC942P

Order Number: AN1934/D

AN1934

Rev 0, 09/2001

Related parts for AN1934

AN1934 Summary of contents

Page 1

... Figure 4 and may or may not have built–in fanout buffers not the intention of this application note to explain all of the fundamentals of a PLL; however, a quick review of the components is covered. Figure 2. Fanout Buffer Go to: www.freescale.com Order Number: AN1934/D Rev 0, 09/2001 AN1934 MPC942P t ...

Page 2

Freescale Semiconductor, Inc. A basic PLL clock architecture (Figure 3) consists of a phase detector, a low pass filter and (in this diagram) two CO, divider networks. Both dividers are at the inputs of the phase detector. The ...

Page 3

Freescale Semiconductor, Inc. Skew Clock fanout buffers and PLL clock drivers with built–in fanout buffers offer multiple outputs. These clock outputs are routed across a PC board to various devices. A typical fanout buffer may have as many as 18 ...

Page 4

Freescale Semiconductor, Inc. ∅ ∅ ∅ ∅ Figure 8. Phase Jitter Jitter Values and Data Sheets Definitions of the various types of jitter and the equations for calculating the values are necessary for an understanding of jitter and how it ...

Page 5

Freescale Semiconductor, Inc. Figure 10. Period Jitter for Typical PLL Clock Device with F PLL Bandwidth and Jitter The PLL based clock driver locks reference frequency and maintains an output frequency based upon that reference frequency. If ...

Page 6

Freescale Semiconductor, Inc. Clock Tree Application Example Analysis Figure 12 shows an example clock tree application which is used to show the effects of skew and jitter in a system. The goal of this design is to provide multiple phase ...

Page 7

Freescale Semiconductor, Inc. Figure 13. Example Clock Tree Analysis without Jitter and Skew The first analysis of the clock tree is with the assumption that there is zero output–to–output skew and zero jitter. With zero skew between the outputs of ...

Page 8

Freescale Semiconductor, Inc. output–to–output skew from the MPC961P. Note that Figure 14 is not to scale and the magnitudes of the skew and jitter are actually much smaller than indicated. Table 2 lists the skew and jitter values for the ...

Page 9

Freescale Semiconductor, Inc. MOTOROLA For More Information On This Product, NOTES Go to: www.freescale.com 9 ...

Page 10

Freescale Semiconductor, Inc. 10 For More Information On This Product, NOTES Go to: www.freescale.com MOTOROLA ...

Page 11

Freescale Semiconductor, Inc. MOTOROLA For More Information On This Product, NOTES Go to: www.freescale.com 11 ...

Page 12

... ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 Technical Information Center: 1–800–521–6274 HOME PAGE: http://www.motorola.com/semiconductors/ ◊ 12 For More Information On This Product, are registered trademarks of Motorola, Inc. Motorola, Inc Equal Go to: www.freescale.com AN1934/D MOTOROLA ...

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