AN1934 Freescale Semiconductor / Motorola, AN1934 Datasheet - Page 3

• Manufacturer Part Number: AN1934
• Description: Effects of Skew and Jitter on Clock Tree Design
• Manufacturer: Freescale Semiconductor / Motorola

Skew
fanout buffers offer multiple outputs. These clock outputs are
routed across a PC board to various devices. A typical fanout
buffer may have as many as 18 to 20 clock outputs. Typically,
these outputs are designed to drive a 50 ohm cable or a 50 ohm
PC board trace. Ideally, all of the outputs are timed such that
clock edges on each output switch at exactly the same time.
However, real life devices do not. Small amounts of skew exist
between the high to low or low to high transition on one output
as compared to another output. For systems that require
synchronization between data and clocks or multiple clocks on
the PC board, this skew is a bad thing. Clock integrated circuit
designers try to minimize the amount of skew in a device.
However, skew does exist and the device data sheet usually
specifies the amount of skew.
output–to–output, process, or part–to–part skew.
various output edges on a single device. Process skew is
defined as the skew between the same output pin on two
different devices. Finally, the part–to–part skew is defined as
the skew between any output on two different devices. Figure
5 illustrates output skew types for both single–ended and
differential output waveforms. Typically, both output–to–output
and part–to–part skew are specified on a data sheet. The
JEDEC specification states that the skew values are to be
determined with the outputs driving identical specified loads.
Jitter
clock buffer. As with skew, jitter is a bad thing and is usually
measured in picoseconds. There are three categories of jitter
that are of interest: cycle–to–cycle, period, and phase jitter.
adjacent clock cycles. The difference is reported as an absolute
value according to the JEDEC specification. However, quite
often a ± value is used. The JEDEC symbol for cycle–to–cycle
jitter is t
large sampling of cycles and specified as the maximum
MOTOROLA
Clock fanout buffers and PLL clock drivers with built–in
This output skew is typically defined in three ways:
Output–to–output skew is defined as the skew between the
Jitter is a deviation of the edge location on the output of the
Cycle–to–cycle jitter is the difference in the period of any two
jit(cc)
. Cycle–to–cycle is usually measured over some
Figure 5. Output–to–Output Skew
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difference. Figure 6 shows the measurement and calculation of
cycle–to–cycle jitter.
is usually small since the PLL does not quickly respond to
changes on its input. Since cycle–to–cycle jitter is the
difference in the period from one cycle to the next, this jitter is
at the clock frequency. This jitter is also referred to as short term
jitter.
within the device. In addition, external sources contribute to this
jitter. Specifically, power supply noise may be a source of jitter
in both PLL based and non–PLL based clock driver devices.
Power supply design, power supply filtering, and board layout
contributes to the overall jitter values measured on the output
of the clock device.
JEDEC specification as the deviation in cycle time of a signal
with respect to an ideal period. Figure 7 shows the definition
and calculation of period jitter. This jitter type is reported as an
absolute maximum value as measured over a long time period.
The JEDEC symbol for period jitter is t
period varies from measurement system to measurement
system. Typical time periods are 64 microseconds which, at a
frequency of 100 MHz or so, yields many (6400) clock cycle
period values. This type of jitter represents the random
movement in the instantaneous output frequency or output
period of the clock source.
is associated with PLL based clock drivers. The JEDEC
specification notation is t
output jitter associated with a PLL clock driver. The value is
given as an absolute value of the range or variation in the
difference between the phase of the reference input and the
phase of the feedback input to the integrated circuit. (See
Figure 8)
In PLL based systems, the value of the cycle–to–cycle jitter
Clock integrated circuits have an inherent jitter generated
The second type of jitter is period jitter, which is defined in the
The last jitter type covered is that of phase jitter. Phase jitter
Figure 6. Cycle–to–Cycle Jitter
Figure 7. Period Jitter
jit(φ)
. This value represents the input to
jit(per)
. The long time
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