AN1934 Freescale Semiconductor / Motorola, AN1934 Datasheet - Page 2

• Manufacturer Part Number: AN1934
• Description: Effects of Skew and Jitter on Clock Tree Design
• Manufacturer: Freescale Semiconductor / Motorola

detector, a low pass filter, a V
divider networks. Both dividers are at the inputs of the phase
detector. The input to the clock driver, or the reference
frequency, may be external or sourced from a crystal oscillator
that is included as part of the clock driver architecture. This
input frequency may be divided by an optional P divider block
and then applied to the input of the phase detector. The phase
detector produces a correction signal based upon the
difference in phase in its two inputs. The correction signal or the
output of the phase detector is filtered and applied to the input
of the voltage controlled oscillator; V
is applied to the M divider and becomes feedback and the
second of the two inputs to the phase detector. When the loop
is in “lock,” the two inputs to the phase detector are the same
frequency and the same phase. The output frequency, or F
is the reference frequency divided by P and then multiplied by
M and will continually track the reference frequency.
can create a multi–frequency and multi–clock distribution
device as shown in Figure 4. The more complex divider network
shown provides the M divide value for the feedback path to the
input of the phase detector and, also, the N divider divides down
the V
frequencies. Multiple outputs from the clock divider may
provide for the generation of multiple frequencies. Note that
fanout buffers are included for each output to provide the
required system clock drive. Also note that an equivalent fanout
buffer is included for the feedback path. The feedback
connection for the PLL is external to the device and thus
equalizes the delay through the main clock outputs. As is
discussed later, the external feedback path may also include
compensating trace delay which allows the phase of F
clock to be advanced forward or backward with respect to the
input clock.
A basic PLL clock architecture (Figure 3) consists of a phase
With a few additions to the basic PLL clock architecture, we
2
CO
frequency to the desired system frequency or
Figure 3. Basic PLL
CO,
and (in this diagram) two
CO
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. The output of the V
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OUT,
OUT
CO
Clock Driver Parametrics
application note are Buffer Propagation Delay, Zero Reference
Delay, Skew, Jitter, and PLL Bandwidth and Jitter. These
parameters are typically found in the AC parameter portion of
a clock driver data sheet.
delay. PLL clock driver devices are characterized with jitter,
output skew, and an effective input to output propagation delay
called Zero Reference Phase Delay. In a clock tree design, the
parameters that complicate the analysis is skew between the
outputs of a clock fanout buffer and edge or frequency jitter.
Jitter commonly is generated in the very early stages of a clock
tree and potentially at each stage of the clock tree. These jitter
sources may or may not be cumulative and be passed to the
outputs.
Buffer Propagation Delay
input to output. Typical values for this delay are in the order of
a few nanoseconds. Data sheet specifications may be given for
a single propagation delay or as separate values given for a low
to high edge; versus a high to low edge. The low to high edge
value and the high to low edge value should be very similar but
not necessarily the same. The notation for propagation delay
is t
propagation delay for a low to high transition and a high to low
transition of a waveform, respectively.
Reference Zero Delay
PLL buffer delay. This parameter is also referred to as Static
Phase Offset (or SPO). The JEDEC notation is t
of SPO is defined as the average difference in phase between
the input reference clock and the feedback input signal, when
the PLL is locked. The value of the Reference Zero Delay can
be compensated for by including PC board trace delay in the
feedback path of the PLL. Specially constructed PLL clock
drivers called Zero–delay Buffers make use of this occurance
and can produce a clock edge at the output that is exactly in
phase with the input.
The clock driver parameters that are of interest in this
Fanout buffers have output skew, jitter, and propagation
Clock distribution buffers have a propagation delay from
Reference Zero Delay is the JEDEC term for the effective
pd
. Also the notations of t
Figure 4. PLL Based Clock Driver
plh
and t
phl
are used to indicate the
MOTOROLA
(φ)
. The value