AN1934 Freescale Semiconductor / Motorola, AN1934 Datasheet - Page 6

• Manufacturer Part Number: AN1934
• Description: Effects of Skew and Jitter on Clock Tree Design
• Manufacturer: Freescale Semiconductor / Motorola

Clock Tree Application Example Analysis
used to show the effects of skew and jitter in a system. The goal
of this design is to provide multiple phase aligned HSTL and
LVCMOS outputs. The reference for this clock tree is a crystal
oscillator while the outputs of the tree provide both HSTL and
LVCMOS to various system locations. The tree starts with a
crystal oscillator in the MC12430 integrated circuit. The
MC12430 is a PLL based clock synthesizer that allows very fine
control of the output frequency in 1 MHz steps.
Figure 12 shows an example clock tree application which is
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Figure 12. Example Clock Tree
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Figure 11. PLL Bandwidth
Modulation Frequency (Hz)






input to the MC100EP111 fanout buffer.
which one pair is connected to a MC100EP223 input and
another pair connected to the MPC961P input. The
MC100EP223 fanout buffer provides HSTL outputs while the
MPC961P is a PLL–based clock generator that provides
several LVCMOS outputs. Notice there is an introduced delay
from the LVPECL output of the EP111 to the LVPECL input of
the MPC961P zero–delay buffer. This introduced delay is due
to backplane or cable distance which will skew the LVCMOS
outputs to later than the HSTL outputs. To compensate for this
delay, the MPC961P zero–delay buffer is used in conjunction
with a PC board delay line in the feedback path.
the situation where we have no (or choose to ignore both) jitter
and skew in the devices. Later, in Figure 14, an analysis with
both jitter and skew is shown. The circled numbers in Figure 12
are used as reference points on the clock analysis waveforms.
The LVPECL output of the MC12430 drives the LVPECL
The MC100EP111 consists of 10 LVPECL differential pairs of
Figure 13 provides an analysis of the example clock tree for
MOTOROLA