CY28412 SpectraLinear, CY28412 Datasheet - Page 2

• Manufacturer Part Number: CY28412
• Description: Clock Generator
• Manufacturer: SpectraLinear

Rev 1.0, November 20, 2006
Pin Definitions
47,46,44,43
39,38
16,17
55, 54
14
42
1,2,5,6,7,8
11
12
49
50
27,28
19,20,21,22,
25,26,30,31,
32,33,35,36
13
45
3,10
56
23,29,37
40
15
48
4,9
53
24,34
41
18
52
51
Pin No.
CPUT/C
CPUT2_ITP/SRCT6,
CPUC2_ITP/SRCC6
DOT96T, DOT96C
REF0/FS_C,
REF1/FS_A
USB48/FS_B
IREF
PCI[0:5]
TEST_SEL/PCIF0
ITP_EN/PCIF1
SCLK
SDATA
SATAT, SATAC
SRCT/C[0:5]
VDD_48
VDD_CPU
VDD_PCI
VDD_REF
VDD_SRC
VDD_A
GND_48
GND_CPU
GND_PCI
GND_REF
GND_SRC
GND_A
VTT_PWRGD#/PD
X1
X2
Name
I/O, SE Free-running 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD#
O, DIF Differential CPU clock outputs.
O, DIF Selectable Differential CPU or SRC clock output.
O, DIF Fixed 96-MHz clock output.
O, DIF Differential serial reference clock. Recommended output for SATA.
O, DIF Differential serial reference clocks.
O, SE 33-MHz clocks.
O, SE 14.318-MHz crystal output.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for PLL.
GND
GND
GND
GND
GND
GND
I, PU
Type
I/O
I/O
I/O
I/O
I
I
I
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC6
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
14.318-MHz reference clock/3.3V-tolerant input for CPU frequency selection.
Input is latched upon assertion (LOW) of VTT_PWRGD#/PD
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Fixed 48-MHz USB clock output/3.3V-tolerant input for CPU frequency
selection.
Input is latched upon assertion (LOW) of VTT_PWRGD#/PD
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
A precision resistor is attached to this pin, which is connected to the
internal current reference.
Free-running 33-MHz clocks/ 3.3V-tolerant input for selecting test mode.
Input is latched upon assertion (LOW) of VTT_PWRGD#/PD
1 = All outputs are three-stated for test
0 = All outputs normal operation
**This input has an internal pull-down resistor.
assertion).
1 = CPU2_ITP, 0 = SRC6
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for PLL.
3.3V LVTTL input is a level sensitive strobe used to latch the REF0/FSC,
REF1/FSA, USB48/FSB, TEST_SEL/PCIF0 and ITP_EN/PCIF1 inputs. After
VTT_PWRGD# (active LOW) assertion, this pin becomes a realtime input for
asserting power-down (active HIGH).
14.318-MHz crystal input.
Description
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CY28412
Page 2 of 16