CY29352 Cypress Semiconductor, CY29352 Datasheet - Page 6

• Manufacturer Part Number: CY29352
• Description: 11 Output Zero Delay Buffer
• Manufacturer: Cypress Semiconductor

www.DataSheet4U.com
AC Parameters
Document Number: 38-07476 Rev. *B
f
f
f
t
f
DC
t
t
t
t
t
BW
t
t
t
t
Note
VCO
in
refDC
r
MAX
(φ)
sk(O)
sk(B)
PLZ, HZ
PZL, ZH
JIT(CC)
JIT(PER)
JIT(φ)
LOCK
Parameter
6. AC characteristics apply for parallel output termination of 50Ω to V
, t
f
by characterization and are not 100% tested.
[6]
VCO frequency
Input frequency
Input duty cycle
TCLK input rise and fall time
Maximum output frequency
Output duty cycle
Propagation delay (static phase
offset)
Output to output skew
Bank to bank skew
Output disable time
Output enable time
PLL closed loop bandwidth
(–3 dB)
Cycle to cycle jitter
Period jitter
IO phase jitter
Maximum PLL lock time
(V
DD
Description
= 3.3V ± 5%, T
A
= –40°C to +85°C)
0.8V to 2.0V
÷2 feedback
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
Bypass mode (PLL_EN# = 1)
÷2 output
÷4 output
÷6 output
÷8 output
÷12 output
f
TCLK to FB_IN, same V
does not include jitter
Skew within each Bank
Banks at same voltage, same
frequency
Banks at same voltage,
different frequency
Banks at different voltage
÷2 feedback
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
Same frequency
Multiple frequencies
Same frequency
Multiple frequencies
VCO < 300 MHz
VCO > 300 MHz
MAX
TT
. Outputs are at the same supply voltage unless otherwise stated. Parameters are guaranteed
< 100 MHz
Condition
DD
,
33.33
16.67
33.33
16.67
–100
Min
200
100
100
50
25
25
50
25
48
0
1–1.5
0.75
Typ
150
100
0.6
0.5
2
83.33
41.67
83.33
41.67
Max
62.5
62.5
500
200
125
200
200
125
200
125
175
235
425
100
275
100
150
1.0
75
52
10
8
1
CY29352
Unit
MHz
MHz
MHz
MHz
Page 6 of 9
ms
ns
ps
ps
ps
ns
ns
ps
ps
ps
%
%
[+] Feedback