AN2492 Freescale Semiconductor / Motorola, AN2492 Datasheet

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AN2492

Manufacturer Part Number
AN2492
Description
MPC184 Descriptor Programmers Guide--PCI View
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
Application Note
AN2492/D
Rev. 0, 6/2003
MPC184 Descriptor
Programmer’s Guide—
PCI View
Geoff Waters
Security Applications
Michael Torla
Security Design
This application note is offered as a supplement to the MPC184 Security Co-Processor User’s
Manual, PCI Interface, to assist the user in understanding and creating descriptors in the event
the user has more specific requirements than those covered by the MPC184 device driver. This
application note will be more useful if the reader is already basically familiar with the
MPC184 architecture, as explained in the user’s manual. All descriptor and execution unit
references are shown in little endian format consistent with the PCI version of the MPC184
user’s manual.
The following topics are addressed:
Topic
Section 1, “Data Packet Descriptor Overview”
Section 2, “Descriptor Structure”
Section 3, “Descriptor Header”
Section 4, “Execution Unit Mode Data”
Section 5, “Descriptor Type Field”
Section 6, “Descriptor Length and Pointer Fields”
Section 7, “Descriptor Chaining”
Section 8, “Descriptor Classes”
Section 9, “Additional Examples”
Section 10, “SSLv3.1/TLS1.0 Processing”
Section 11, “Conclusion”
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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AN2492 Summary of contents

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... Freescale Semiconductor, Inc. Application Note AN2492/D Rev. 0, 6/2003 MPC184 Descriptor Programmer’s Guide— PCI View Geoff Waters This application note is offered as a supplement to the MPC184 Security Co-Processor User’s Security Applications Manual, PCI Interface, to assist the user in understanding and creating descriptors in the event the user has more specific requirements than those covered by the MPC184 device driver ...

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Freescale Semiconductor, Inc. Data Packet Descriptor Overview Data Packet Descriptor Overview 1 Data Packet Descriptor Overview The MPC184 has bus mastering capability on either 32-bit PCI or the PowerQUICC 8xx bus to off-load data movement and encryption operations from a ...

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Freescale Semiconductor, Inc. 3 Descriptor Header Descriptors are created by the host to guide the MPC184 through required cryptographic operations. The descriptor header defines the operations to be performed, the mode for each operation, and the ordering of the inputs ...

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Freescale Semiconductor, Inc. Execution Unit Mode Data Execution Unit Mode Data Table 1. Header Bit Definitions (continued) Bits Name 0 DN DONE_NOTIFICATION_FLAG—Done Notification Flag Setting this bit indicates whether to perform notification on completion of this descriptor. The notification can ...

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Freescale Semiconductor, Inc. of the MPC184 Security Co-Processor User’s Manual, PCI Interface, however, the mode register for each EU is provided in this section for convenience. 4.1 PKEU Mode Register This register specifies the internal PKEU routine to be executed. ...

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Freescale Semiconductor, Inc. Execution Unit Mode Data Execution Unit Mode Data Table 3. Mode Register Routine Definitions Routine Reserved Clear memory Modular exponentiation 2 R mod mod affine point multiplication ...

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Freescale Semiconductor, Inc. 31 Field Reserved Reset 0 R/W Addr 31 Field Reset R/W Addr Table 4 describes the DEU mode register signals. Table 4. DEU Mode Register Signals Bits Signal 31:11 — Reserved 10:8 Burst size The MPC184 implements ...

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Freescale Semiconductor, Inc. Execution Unit Mode Data Execution Unit Mode Data 4.3.1 Host-Provided Context via Prevent Permute In the default mode of operation, the host provides the key and key size to the AFEU. The initial memory values in the ...

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Freescale Semiconductor, Inc. Table 5 describes the AFEU mode register signals. Table 5. AFEU Mode Register Signals Bits Signal 31:11 — Reserved 10:8 Burst size The MPC184 implements flow control to allow larger than FIFO sized blocks of data to ...

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Freescale Semiconductor, Inc. Execution Unit Mode Data Execution Unit Mode Data Figure 8 shows the MDEU mode register. 31 Field Reserved Reset R/W Addr 31 Field Reset R/W Addr Table 6 describes the MDEU mode register signals. Bits Signal 31:11 ...

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Freescale Semiconductor, Inc. Table 6. MDEU Mode Register (continued) Bits Signal set, configures the MDEU to automatically pad partial message blocks not autopad 1 Perform automatic message padding whenever an incomplete message block is detected ...

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Freescale Semiconductor, Inc. Execution Unit Mode Data Execution Unit Mode Data 4.5 RNG Mode Register The RNG mode register is used to control the RNG. One operational mode, randomizing, is defined. Writing any other value than 0 to 7:0 results ...

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Freescale Semiconductor, Inc Field Reserved Reset R/W Addr Table 8 describes the AESU mode register signals. Table 8. AESU Mode Register Signals Bits Signal 31:11 — Reserved 10:8 Burst size The MPC184 implements flow control to allow larger ...

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Freescale Semiconductor, Inc. Descriptor Type Field Descriptor Type Field To use RDK, the following procedure is recommended: • The descriptor type used in decryption of the first portion of the message is ‘0100—AESU Key Expand Output.’ The description mode must ...

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Freescale Semiconductor, Inc. Table 9. Descriptor Types (continued) 1011 pkeu_static_ec_parameter 1100 Reserved 1101 Reserved 1110 hmac_snoop_afeu_ key_in 1111 hmac_snoop_afeu_ctx_in Table 10 shows how the length/pointer pairs should be used with the various descriptor types to load keys, context, and data ...

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Freescale Semiconductor, Inc. Descriptor Type Field Descriptor Type Field Table 11. Descriptor Type 0001 Length/Pointer Mapping Descriptor L/P 1 L/P 2 Type 0001 Null Null 0001 Null Ctx-in (opt) 0001 Null Ctx-in (opt) 0001 Null IV For RNG operations, there ...

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Freescale Semiconductor, Inc. In-FIFO DEU Out-FIFO In-Snooping 5.3 Done Notification Bit The done notification bit in the MPC184 descriptor header acts as a manual override to the crypto-channel configuration register’s NOTIFICATION_TYPE bit. The NOTIFICATION_TYPE bit determines whether the MPC184 will ...

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Freescale Semiconductor, Inc. Descriptor Length and Pointer Fields Descriptor Length and Pointer Fields 31 Field Reserved Reset R/W Figure 12. Descriptor Length Field Table 12 shows the descriptor length field mapping. Table 12. Descriptor Length Field Mapping Bits Name Reset ...

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Freescale Semiconductor, Inc. 31 Field Reset R/W Figure 14. Next Descriptor Pointer Field Table 14 describes the descriptor pointer field mapping. Table 14. Descriptor Pointer Field Mapping Bits Name Reset Value 31:0 Next descriptor 0 pointer 7 Descriptor Chaining Descriptor ...

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Freescale Semiconductor, Inc. Descriptor Classes Descriptor Classes DPD–DES–CTX_CRYPT DPD–DES–CTX_CRYPT LEN_CTXIN LEN_CTXIN PTR_CTXIN PTR_CTXIN LEN_KEY LEN_KEY PTR_KEY PTR_KEY LEN_DATAIN LEN_DATAIN PTR_DATAIN PTR_DATAIN LEN_DATAOUT LEN_DATAOUT PTR_DATAOUT PTR_DATAOUT LEN_CTXOUT LEN_CTXOUT PTR_CTXOUT PTR_CTXOUT nul length nul length nul pointer nul pointer nul length nul ...

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Freescale Semiconductor, Inc. multiple subsequent) descriptor contains length/pointer pairs to the data to be permuted. Because the key and context are unchanging over multiple packets (or descriptors), the series of short reads and writes required to setup and tear down ...

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Freescale Semiconductor, Inc. Descriptor Classes Descriptor Classes Table 16. Actual Descriptor DPD_Type 0001_3DES_CBC_Encrypt (continued) Field Value/Type LEN_2 Length PTR_2 Pointer LEN_3 Length PTR_3 Pointer LEN_4 Length PTR_4 Pointer LEN_5 Length PTR_5 Pointer LEN_6 Nul PTR_6 Nul LEN_7 Nul PTR_7 Nul ...

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Freescale Semiconductor, Inc. Table 17. Actual Descriptor DPD_Type 0001_3DES_CBC_Encrypt (continued) Field Value/Type PTR_7 Nul PTR_NEXT Pointer 8.2 Dynamic Descriptors In a typical networking environment, packets from innumerable sessions arrive fairly randomly. The host must determine which security association applies to ...

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Freescale Semiconductor, Inc. Additional Examples Additional Examples Note that the descriptor header value is the same as the value used in the static assignment example. The descriptor header does not determine static vs. dynamic assignment (this is a difference from ...

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Freescale Semiconductor, Inc. Table 19. Representative Descriptor DPD_Type 0010_3DES_CBC_HMAC_SHA-1_Decrypt (continued) Field Value/Type PTR_7 Pointer PTR_NEXT Pointer The descriptor header encodes the information required to select the DEU for Op_0, and the MDEU for Op_1. The Op_0 mode data configured the ...

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Freescale Semiconductor, Inc. Additional Examples Additional Examples Table 20. Representative Descriptor DPD_Type 0010_3DES_CBC_HMAC_SHA-1_Decrypt (continued) Field Value/Type LEN_4 Length PTR_4 Pointer LEN_5 Length PTR_5 Pointer LEN_6 Length PTR_6 Pointer LEN_7 Length PTR_7 Pointer PTR_NEXT Pointer The descriptor header encodes the information ...

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Freescale Semiconductor, Inc. Table 21. Representative Descriptor DPD_Type 0001_HMAC-MD-5 Field Value / Type Header 0x31E0_0010 LEN_1 Length PTR_1 Pointer LEN_2 Length PTR_2 Pointer LEN_3 Length PTR_3 Pointer LEN_4 Length PTR_4 Pointer LEN_5 Length PTR_5 Pointer LEN_6 Length PTR_6 Pointer LEN_7 ...

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Freescale Semiconductor, Inc. Additional Examples Additional Examples Table 22. Common IPSec Dynamic Descriptor Headers Value/Type 0x2003_1E22 DPD_Type 0010_DES_ECB_HMAC_MD-5 Decrypt 0x2013_1E20 DPD_Type 0010_DES_ECB_HMAC_MD-5 Encrypt 0x2003_1C22 DPD_Type 0010_DES_ECB_HMAC_SHA-1 Decrypt 0x2013_1C20 DPD_Type 0010_DES_ECB_HMAC_SHA-1 Encrypt 0x2043_1E22 DPD_Type 0010_3DES_ECB_HMAC_MD-5 Decrypt 0x2053_1E20 DPD_Type 0010_3DES_ECB_HMAC_MD-5 Encrypt 0x2043_1C22 ...

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Freescale Semiconductor, Inc. Table 23. Additional Multi-Op Dynamic Descriptor Headers (continued) Value / Type 0x60A3_1D22 DPD_Type 0010_AES_CBC_HMAC_SHA-256 Decrypt 0x60B3_1D20 DPD_Type 0010_AES_CBC_HMAC_SHA-256 Encrypt 0x60E3_1E22 DPD_Type 0010_AES_CTR_HMAC_MD-5 Decrypt 0x60E3_1E20 DPD_Type 0010_AES_CTR_HMAC_MD-5 Encrypt 0x60E3_1C22 DPD_Type 0010_AES_CTR_HMAC_SHA-1 Decrypt 0x60E3_1C20 DPD_Type 0010_AES_CTR_HMAC_SHA-1 Encrypt 0x60E3_1D22 DPD_Type ...

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Freescale Semiconductor, Inc. Additional Examples Additional Examples Table 24. Representative First Descriptor DPD_Type 0010_3DES_CBC_HMAC_SHA-1_Decrypt (continued) Field Value / Type PTR_7 Nul PTR_NEXT Pointer The first descriptor header encodes the information required to select the DEU for Op_0, and the MDEU ...

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Freescale Semiconductor, Inc. Table 25. Representative Middle Descriptor DPD_Type 0010_3DES_CBC_HMAC_SHA-1 Decrypt (continued) Field Value/Type PTR_7 Nul PTR_NEXT Pointer The middle descriptor header encodes the information required to select the DEU for Op_0, and the MDEU for Op_1. The Op_0 mode ...

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Freescale Semiconductor, Inc. Additional Examples Additional Examples The final descriptor header encodes the information required to select the DEU for Op_0, and the MDEU for Op_1. The Op_0 mode data configured the DEU to operate in 3DES, CBC, decrypt mode. ...

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Freescale Semiconductor, Inc. Table 27. Common IPSec Static Descriptor Headers (continued) Value/Type 0x2053_9A22 DPD_Type 0010_3DES_ECB_HMAC_MD-5 Encrypt First 0x2053_8220 DPD_Type 0010_3DES_ECB_HMAC_MD-5 Encrypt Middle 0x2053_8E20 DPD_Type 0010_3DES_ECB_HMAC_MD-5 Encrypt Last 0x2043_9822 DPD_Type 0010_3DES_ECB_HMAC_SHA-1 Decrypt First 0x2043_8022 DPD_Type 0010_3DES_ECB_HMAC_SHA-1 Decrypt Middle 0x2043_8C22 DPD_Type 0010_3DES_ECB_HMAC_SHA-1 ...

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Freescale Semiconductor, Inc. SSLv3.1/TLS1.0 Processing SSLv3.1/TLS1.0 Processing 10 SSLv3.1/TLS1.0 Processing The MPC184 is capable of assisting in SSL record layer processing, however, for SSL v3.0 and earlier, this support is limited to acceleration of the encryption only. The MDEU does ...

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Freescale Semiconductor, Inc. Table 28. Outbound TLS Descriptor 1 (continued) Field Value/Type PTR_5 Pointer LEN_6 Length PTR_6 Pointer LEN_7 Length PTR_7 Pointer PTR_NEXT Pointer The primary EU is the MDEU, with its mode bits set to cause the MDEU to ...

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Freescale Semiconductor, Inc. SSLv3.1/TLS1.0 Processing SSLv3.1/TLS1.0 Processing Not surprisingly, inbound TLS processing reverses the order of operations of outbound processing. 10.3 Inbound TLS Descriptor 1 The first descriptor performs the decryption of the record, HMAC, pad length, and any padding ...

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Freescale Semiconductor, Inc. 10.4 Inbound TLS Descriptor 2 The second descriptor performs the HMAC of the record header and the record payload. In the example shown in Table 31, the HMAC is generated using the MD-5 algorithm. Table 31. Inbound ...

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Freescale Semiconductor, Inc. Conclusion Conclusion THIS PAGE INTENTIONALLY LEFT BLANK 38 MPC184 Descriptor Programmer’s Guide— PCI View For More Information On This Product, Go to: www.freescale.com MOTOROLA ...

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Freescale Semiconductor, Inc. THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA MPC184 Descriptor Programmer’s Guide— PCI View For More Information On This Product, Go to: www.freescale.com Conclusion 39 ...

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... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2003 AN2492/D For More Information On This Product, Go to: www.freescale.com ...

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