AN2492 Freescale Semiconductor / Motorola, AN2492 Datasheet - Page 29

• Manufacturer Part Number: AN2492
• Description: MPC184 Descriptor Programmers Guide--PCI View
• Manufacturer: Freescale Semiconductor / Motorola

9.4 Statically Assigned 3DES-HMAC-SHA-1 Decrypt (Inbound
This example, shown in Table 24, is designed to contrast the dynamic descriptor shown in Table 19. For
whatever reason, the data to be decrypted and authenticated is not available in a single contiguous block, or
the total data size is larger than 32 Kbytes. The user must statically assign a DEU and MDEU to a channel
before launching this descriptor chain.
The first descriptor loads the appropriate keys and context, while the N middle descriptors continue
processing data. The final descriptor decrypts the final data, and allows the HMAC calculation to complete.
MOTOROLA
Header
LEN_1
PTR_1
LEN_2
PTR_2
LEN_3
PTR_3
LEN_4
PTR_4
LEN_5
PTR_5
LEN_6
PTR_6
LEN_7
IPSec ESP)
Field
Table 23. Additional Multi-Op Dynamic Descriptor Headers (continued)
0x60A3_1D22
0x60B3_1D20
0x60E3_1E22
0x60E3_1E20
0x60E3_1C22
0x60E3_1C20
0x60E3_1D22
0x60E3_1D20
Value / Type
MPC184 Descriptor Programmer’s Guide— PCI View
Table 24. Representative First Descriptor DPD_Type
Freescale Semiconductor, Inc.
0x2063_9822
Value / Type
For More Information On This Product,
0010_3DES_CBC_HMAC_SHA-1_Decrypt
Pointer
Pointer
Pointer
Pointer
Pointer
Pointer
Length
Length
Length
Length
Length
Length
Nul
DPD_Type 0010_AES_CBC_HMAC_SHA-256 Decrypt
DPD_Type 0010_AES_CBC_HMAC_SHA-256 Encrypt
DPD_Type 0010_AES_CTR_HMAC_MD-5 Decrypt
DPD_Type 0010_AES_CTR_HMAC_MD-5 Encrypt
DPD_Type 0010_AES_CTR_HMAC_SHA-1 Decrypt
DPD_Type 0010_AES_CTR_HMAC_SHA-1 Encrypt
DPD_Type 0010_AES_CTR_HMAC_SHA-256 Decrypt
DPD_Type 0010_AES_CTR_HMAC_SHA-256 Encrypt
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DPD_Type 0010_3DES_CBC_HMAC_SHA-1_Decrypt
Number of bytes of HMAC key to be written to MDEU key register
PCI address of HMAC key
Number of bytes to be hashed
PCI address of data to be hashed
Number of bytes of key to be written to DEU key register (must be
16 or 24)
PCI address of key
Number of bytes of IV to be written to DEU IV register (always 8)
PCI address of IV
Number of bytes to be ciphered
PCI address of data to be ciphered
Bytes to be written (should be equal to length of data-in)
PCI address where ciphered data is to be written
Null
Description
Description
Additional Examples
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