AN2502 Freescale Semiconductor / Motorola, AN2502 Datasheet - Page 31

• Manufacturer Part Number: AN2502
• Description: Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI
• Manufacturer: Freescale Semiconductor / Motorola

NoTxPending:
;**********************************************************************
;* This ISR is dedicated for reception.
;* When the receiving line is in idle state, this channel is
;* configured as input capture on falling edge, waiting for a start
;* bit. When the start bit is received, the channel is configured as
;* output compare with pins under port control, since the output
;* compare will be used only as a timing reference for the bits
;* reception. In the first data bit reception, the time added to the
;* reception channel is 1.3 bit time minus 26 of pin check latency,
;* so the instruction that check the pin state does not check the
;* state in the bit time boundary. This latency is measured from the
;* beginning of the ISR to the instruction that checks the pin state. *
;* In each consecutive output compare the pin state is read and
;* shifted into the reception shift register. When all the data bits
;* are received, the stop bit is ignored and the channel is
;* again configured as input capture on falling edges to detect the
;* next start bit
;**********************************************************************
RX_isr:
MOTOROLA
TAX
PSHH
PULA
ADC
PSHA
PULH
STHX
BRA
CLR
PULH
RTI
PSHH
BCLR
BRSET
BSET
MOV
LDHX
TXA
ADD
TAX
PSHH
PULA
ADC
Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI
#BITHI
TCH1H
oc_low
TSC1
CH0F,TSC0 ; 4........ [4 CYCLES]
RPF,rSCSR,rxinprog
RPF,rSCSR ; set receive in progress flag. Program
#$80,rSCRSR
TCH0H
#BIT1LO
#BIT1HI
Freescale Semiconductor, Inc.
For More Information On This Product,
; Send start bit for pending Tx
; Disable transmission Channel
; 2........ [9 CYCLES Interrupt Entrance]
; 3........ [2 CYCLES]
; 5........ [5 Cycles]
; check if Rx in progress
; goes here if no transmission is in
; progress.
; Store $80 which represents a stop bit
; after 8 transmission bits.
; Since this is the first time we enter
; the ISR for the reception, a 1.3 bit
; time minus pin check latency must be
; added to the channel register.
; Add 1.3 bit time minus pin check lat.
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AN2502/D
Software
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