AN2502 Freescale Semiconductor / Motorola, AN2502 Datasheet - Page 48

• Manufacturer Part Number: AN2502
• Description: Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI
• Manufacturer: Freescale Semiconductor / Motorola

AN2502/D
NoTxPending:
TxPending:
EXITTX:
;**********************************************************************
;* This ISR is dedicated for reception.
;* When the receiving line is in idle state, this channel is
;* configured as input capture on falling edge, waiting for a start
;* bit. When the start bit is received, the channel is configured as
;* output compare with pins under port control, since the output
;* compare will be used only as a timing reference for the bits
;* reception. In the first data bit reception, the time added to the
;* reception channel is 1.3 bit time minus 31 of pin check latency,
;* so the instruction that check the pin state does not check the
;* state in the bit time boundary. This latency is measured from the
;* beginning of the ISR to the instruction that checks the pin state. *
;* In each consecutive output compare the pin state is read and
;* shifted into the reception shift register. When all the data bits
;* are received, the parity is received if enabled and one or two
;* stop bits are received. The channel is again configured as input
;* capture on falling edges to detect the next start bit
;**********************************************************************
RX_isr:
RxNoExit:
48
BRA
CLR
PULH
BRCLR TIEN,rSCCR,EXITTX
JMP
RTI
BCLR
BRSET REN,rSCCR,RxNoExit
JMP
PSHH
BRSET RPF,rSCSR1,rxinprog
BSET
LDA
AND
Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI
TxPending
TSC1
SCITXEMPTY
CH0F,TSC0
RXEXIT
RPF,rSCSR1
rSCSR2
#$32
Freescale Semiconductor, Inc.
For More Information On This Product,
; with interrupt enabled
; Clear pin on output compare to send
; the start bit
; If a transmission is pending, the
; channel is not disabled
; Disable tx channel
; If enabled, jump to tx done
; subroutine
; Else exit
; 2........ [9 CYCLES Interrupt Entrance]
; 3........ [4 CYCLES]
; acknowledge interrupt
; 4........ [5 CYCLES]
; Exits from interrupt if receptions
; are not enabled
; 5........ [2 CYCLES]
; Program goes here if receptions are
; enabled
; 6........ [5 CYCLES]
; check if Rx in progress
; set reception in progress flag
; if there is no reception in progress
; Clear RX Flags in rSCSR2 for the new
; reception
Go to: www.freescale.com
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
MOTOROLA