AN2502 Freescale Semiconductor / Motorola, AN2502 Datasheet - Page 8

• Manufacturer Part Number: AN2502
• Description: Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI
• Manufacturer: Freescale Semiconductor / Motorola

AN2502/D
Reception in
Normal Mode
8
Using Two Channels of the HC08 TIM to Achieve a Full-Duplex Software SCI
Figure 13. SCI Transmit Data Registers (rSCTSRH:rSCTSRL)
The number of bits used in the data registers is configured in the character
length selection bit (M) in rSCCR.
It is possible to implement full-duplex operation because two independent
channels of the TIM are used for each of the operations with independent data
registers.
Figure 14
First the channel is configured for input capture on falling edges. When this
edge is detected, an interrupt service routine is asserted and serviced. Ideally,
a UART (universal asynchronous receiver/transmitter) performs an
over-sampling technique to ensure data integrity. In software-implemented
SCIs, only one pin check per received bit is performed. The time at which this
event occurs is stored in the reception channel registers by the internal
hardware of the MCU. This value will be used for subsequent data bit
receptions.
In the interrupt service routine (ISR) for the input capture, the time for the first
received bit is set. At this point, the reception channel is configured as output
compare and used as a time base for data bit receptions. Because the input
capture interrupt gives a time located in a bit boundary, more than 1 bit-time
Read:
Read:
Write:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
Bit 15
Bit 7
TS7
is a timing diagram of the start bit reception.
Go to: www.freescale.com
= Unimplemented or Reserved
TS6
14
6
RECEPTION CHANNEL
CONFIGURED AS
INPUT CAPTURE
ON FALLING EDGES
Figure 14. Receiving the Start Bit
TS5
13
5
IDLE LINE
TS4
12
4
EDGE DETECTED.
EVENT TIME STORED
IN CHANNEL REGISTERS
START BIT
TS3
11
3
TS2
10
2
TS1
9
1
MOTOROLA
Bit 8
Bit 0
TS8
TS0