EM6517 ETC, EM6517 Datasheet - Page 36

• Manufacturer Part Number: EM6517
• Description: 4 BIT MICROCONTROLLER
• Manufacturer: ETC

11 EEPROM ( 64
The EEPROM addressing is indirect using 6 bits (64 addresses) defined in RegEEPAdr and RegEEPCntl
registers. The EEPROM consist of 2 pages 32x8bit each, address EEPAdr[4 :0]. The page is selected in the
RegEEPCntl register bit EEPage. So the user can address the EEPROM as it would be one block of 64x8 bit.
Any access to the EEPROM is done in two phases. 1
needs to start the desired action, read or write. Refer to the examples below..
How to read data from EEPROM :
1
2
3
4
5
The two last instructions can be executed in the reverse order.
How to write data in EEPROM :
1
2
3
4
5
The three first instructions can be executed in any order.
Writing RegEEPCntl register starts automatically EEPROM reading or writing operation according to the bit
EEPRdWr.
EEPROM writing operation lasts 24ms (Erase followed by write). The flag EEPBusy in RegEEPCntl register
stays high until the writing operation is finished. An interrupt request IRQEEP is generated at the end of each
writing operation. While EEPBusy is high the EEPROM must not be used at all. The EEPROM interrupt request
can be masked (default) (MaskIRQEEP bit). See also the interrupt handling section 13 for further information .
Note : Any Reset or sleep mode will immediately cancel the EEPROM write operation.
© EM Microelectronic-Marin SA, 09/99, Rev. A/277
36
Figure 27. Read Timing 32kHz operation
st
nd
rd
th
th
st
nd
rd
th
th
EE Stable Data
.
inst.
inst.
inst.
inst.
inst.
inst.
inst.
inst.
inst.
CPU Phase
Sys. Clock
The data to be stored at this time may be corrupted.
EE Read
: write EEPROM address (4 low bits) in RegEEPAddr register.
: write the high address bit, page and select reading operation in RegEEPCntl.
: NOP instruction in case of 128kHz operation (metal option setting).
: read EEPROM low data in RegEEPDataL register.
: read EEPROM high data in RegEEPDataH register.
: write EEPROM address (4 low bits) in RegEEPAdr register.
: write EEPROM low data in RegEEPDataL register.
: write EEPROM high data in RegEEPDataH register.
: write the high address bit, page and select writing operation in RegEEPCntl.
: IRQEEP is generated at the end of write.
(EEPAdr[4], EEPage, EEPRdWr=1)
(EEPAdr[4], EEPage, EEPRdWr=0)
8 Bit )
1 2
FOR ENGINEERING ONLY
3
Max. 20 s
4
1
2
3
4
st
, one needs to define the address location. 2
EEPROM access time is max. 20µs : Data is
available in RegEEPDataL and RegEEPDataH
registers at the instruction following the read
access on 32kHz system clock The read signal is
1.5 system clock wide. The CPU reads at end of
phase 3.
With the 128kHz metal option the EERead signal
is 3.5 system clock cycles wide. Using this option
the user must use a NOP instruction before
actually reading the RegEEPDataL,H values.
EM6517
nd
, one