IDT72V3612L12PFG IDT, Integrated Device Technology Inc, IDT72V3612L12PFG Datasheet - Page 10

• Manufacturer Part Number: IDT72V3612L12PFG
• Description: IC FIFO 64X36X2 12NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3612L12PFG

• Function: Asynchronous
• Memory Size: 4.6K (64 x 36 x2)
• Data Rate: 83MHz
• Access Time: 12ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 72V3612L12PFG

SIGNAL DESCRIPTIONS
RESET
least four port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH
transitions. The Reset input can switch asynchronously to the clocks. A
device reset initializes the internal read and write pointers of each FIFO and
forces the Full Flags (FFA, FFB) LOW, the Empty Flags (EFA, EFB) LOW,
the Almost-Empty flags (AEA, AEB) LOW and the Almost-Full flags (AFA,
AFB) HIGH. A reset also forces the Mailbox Flags (MBF1, MBF2) HIGH.
After a reset, FFA is set HIGH after two LOW-to-HIGH transitions of CLKA
and FFB is set HIGH after two LOW-to-HIGH transitions of CLKB. The
device must be reset after power up before data is written to its memory.
Almost-Empty registers (X) with the values selected by the Flag Select (FS0,
FS1) inputs. The values that can be loaded into the registers are shown in
TABLE 1 – FLAG PROGRAMMING
TABLE 2 – PORT-A ENABLE FUNCTION TABLE
TABLE 3 – PORT-B ENABLE FUNCTION TABLE
IDT72V3612 3.3V, CMOS SyncBiFIFO
64 x 36 x 2
The IDT72V3612 is reset by taking the Reset (RST) input LOW for at
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
CSA
CSB
FS1
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
FS0
W/RA
W/RB
H
H
L
L
H
H
H
H
H
H
X
L
L
L
L
X
L
L
L
L
RST
↑
↑
↑
↑
ENA
ENB
H
H
H
H
H
H
H
H
X
L
L
L
X
L
L
L
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
ALMOST-FULL AND
TM
MBA
MBB
X
X
H
H
H
X
X
H
H
H
L
L
L
L
L
L
16
12
8
4
CLKA
CLKB
X
X
↑
↑
X
↑
X
↑
X
X
↑
↑
X
↑
X
↑
10
Data A (A0-A35) I/O
Data B (B0-B35) I/O
Table 1. For the relevant Reset and preset value loading timing diagram, see
Figure 2.
FIFO WRITE/READ OPERATION
Select (CSA) and the port A Write/Read select (W/RA). The A0-A35 outputs
are in the high-impedance state when either CSA or W/RA is HIGH. The A0-
A35 outputs are active when both CSA and W/RA are LOW.
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA
is LOW, and FFA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW,
ENA is HIGH, MBA is LOW, and EFA is HIGH (see Table 2). Relevant Write
and Read timing diagrams for Port A can be found in Figure 3 and Figure
6.
the port B data (B0-B35) outputs is controlled by the port B Chip Select
(CSB) and the port B Write/Read select (W/RB). The B0-B35 outputs are
in the high-impedance state when either CSB or W/RB is HIGH. The B0-
B35 outputs are active when both CSB and W/RB are LOW.
transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB
is LOW, and FFB is HIGH. Data is read from FIFO1 to the B0-B35 outputs
by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB
is HIGH, MBB is LOW, and EFB is HIGH (see Table 3). Relevant Write and
Read timing diagrams for Port B can be found in Figure 4 and Figure 5.
(CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling write
The state of port A data A0-A35 outputs is controlled by the port A Chip
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
The port B control signals are identical to those of port A. The state of
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
The setup and hold time constraints to the port clocks for the port Chip Selects
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
COMMERCIAL TEMPERATURE RANGE
Mail2 Read (Set MBF2 HIGH)
Mail1 Read (Set MBF1 HIGH)
Port Functions
Port Functions
FIFO2 Read
FIFO1 Write
FIFO2 Write
FIFO1 read
Mail1 Write
Mail2 Write
None
None
None
None
None
None
None
None
FEBRUARY 12, 2009