IDT72V3612L12PFG IDT, Integrated Device Technology Inc, IDT72V3612L12PFG Datasheet - Page 19

• Manufacturer Part Number: IDT72V3612L12PFG
• Description: IC FIFO 64X36X2 12NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3612L12PFG

• Function: Asynchronous
• Memory Size: 4.6K (64 x 36 x2)
• Data Rate: 83MHz
• Access Time: 12ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 72V3612L12PFG

NOTE:
1. t
NOTES:
1. t
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
A0 - A35
B0 - B35
CLKA
CLKB
IDT72V3612 3.3V, CMOS SyncBiFIFO
64 x 36 x 2
ENA
AEB
ENB
rising CLKB edge is less than t
rising CLKB edge is less than t
SKEW1
SKEW2
CLKA
W/RA
CLKB
W/RB
MBA
MBB
CSA
ENA
CSB
ENB
EFA
FFB
is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and
LOW
LOW
LOW
LOW
FIFO2 Full
HIGH
HIGH
Previous Word in FIFO2 Output Register
t
CLKH
t
ENS2
SKEW1
SKEW2
t
CLK
t
ENS2
, then FFB may transition HIGH one CLKB cycle later than shown.
, then AEB may transition HIGH one CLKB cycle later than shown.
t
CLKL
Figure 10. FFB
t
TM
SKEW2
t
ENH2
X Words in FIFO1
Figure 11. Timing for AEB
FFB
FFB
FFB
FFB Flag Timing and First Available Write when FIFO2 is Full
t
SKEW1
t
t
ENH2
A
(1)
(1)
1
1
t
CLKH
AEB
AEB when FIFO1 is Almost Empty
AEB
AEB
t
19
CLK
t
CLKL
2
t
PAE
2
Next Word From FIFO2
t
WFF
t
t
ENS2
ENS3
t
DS
COMMERCIAL TEMPERATURE RANGE
To FIFO2
(X+1) Words in FIFO1
t
ENS2
t
WFF
t
t
t
DH
ENH3
ENH2
FEBRUARY 12, 2009
t
t
ENH2
PAE
4659 drw 14
4659 drw 13