IDT72V3612L12PFG IDT, Integrated Device Technology Inc, IDT72V3612L12PFG Datasheet - Page 2

• Manufacturer Part Number: IDT72V3612L12PFG
• Description: IC FIFO 64X36X2 12NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3612L12PFG

• Function: Asynchronous
• Memory Size: 4.6K (64 x 36 x2)
• Data Rate: 83MHz
• Access Time: 12ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 72V3612L12PFG

directional clocked FIFO memory. It supports clock frequencies up to 83 MHz
and has read access times as fast as 8ns. The FIFO operates in IDT Standard
mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip
buffer data in opposite directions. Each FIFO has flags to indicate empty and
full conditions and two programmable flags (Almost-Full and Almost-Empty) to
indicate when a selected number of words is stored in memory. Communication
between each port can bypass the FIFOs via two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been stored. Parity is
checked passively on each port and may be ignored if not desired. Parity
generation can be selected for data read from each port. Two or more devices
can be used in parallel to create wider data paths.
synchronous interface. All data transfers through a port are gated to the LOW-
PIN CONFIGURATIONS
NOTES:
1.
2. NC - No internal connection.
3. Uses Yamaichi socket IC51-1324-828.
IDT72V3612 3.3V, CMOS SyncBiFIFO
64 x 36 x 2
Electrical pin 1 in center of beveled edge.
This device is a clocked FIFO, which means each port employs a
GND
GND
GND
GND
GND
AEA
EFA
V
V
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
CC
A
A
A
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
1
2
3
4
5
6
7
8
9
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TM
PQFP
(3)
(PQ132-1, order code: PQF)
TOP VIEW
2
to-HIGH transition of a port clock by enable signals. The clocks for each port
are independent of one another and can be asynchronous or coincident. The
enables for each port are arranged to provide a simple bi-directional interface
between microprocessors and/or buses with synchronous control.
two-stage synchronized to the port clock that writes data to its array. The Empty
Flag (EFA, EFB) and Almost-Empty (AEA, AEB) flag of a FIFO are two stage
synchronized to the port clock that reads data from its array.
temperature range (–40°C to +85°C) is available by special order. This device
is fabricated using IDT's high speed, submicron CMOS technology.
The Full Flag (FFA, FFB) and Almost-Full (AFA, AFB) flag of a FIFO are
The IDT72V3612 is characterized for operation from 0°C to 70°C. Industrial
COMMERCIAL TEMPERATURE RANGE
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
4659 drw 02
GND
AEB
EFB
GND
GND
GND
GND
B
B
B
B
B
B
B
V
B
B
B
B
B
V
B
B
B
B
B
B
B
B
B
B
B
B
0
1
2
3
4
5
6
CC
7
8
9
10
11
CC
12
13
14
15
16
17
18
19
20
21
22
23
FEBRUARY 12, 2009