IDT72V3612L12PFG IDT, Integrated Device Technology Inc, IDT72V3612L12PFG Datasheet - Page 4

• Manufacturer Part Number: IDT72V3612L12PFG
• Description: IC FIFO 64X36X2 12NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3612L12PFG

• Function: Asynchronous
• Memory Size: 4.6K (64 x 36 x2)
• Data Rate: 83MHz
• Access Time: 12ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 72V3612L12PFG

PIN DESCRIPTION
IDT72V3612 3.3V, CMOS SyncBiFIFO
64 x 36 x 2
A0-A35
AEA
AEB
AFA
AFB
B0-B35
CLKA
CLKB
CSA
CSB
EFA
EFB
ENA
ENB
FFA
FFB
FS1, FS0
MBA
MBB
MBF1
Symbol
Port A Data
Port A Almost-Empty
Flag
Port B Almost-Empty
Flag
Port A Almost-Full
Flag
Port B Almost-Full
Flag
Port B Data.
Port A Clock
Port B Clock
Port A Chip Select
Port B Chip Select
Port A Empty Flag
Port B Empty Flag
Port A Enable
Port B Enable
Port A Full Flag
Port B Full Flag
Flag Offset Selects
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register Flag
Name
(Port A) locations in FIFO1 is less than or equal to the value in the offset register, X.
(Port B) locations in FIFO2 is less than or equal to the value in the offset register, X.
(Port A) and reads from its memory are disabled. Data can be read from FIFO2 to the output register
(Port B) empty, and reads from its memory are disabled. Data can be read from FIFO1 to the output
(Port A) and writes to its memory are disabled. FFA is forced LOW when the device is reset and is set
(Port B) and writes to its memory are disabled. FFB is forced LOW when the device is reset and is set
(Port A) the FIFO2 is less than or equal to the value in the offset register, X.
(PortB)
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
TM
I
I
I
I
I
I
I
I
I
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in
FIFO1 is less than or equal to the value in the offset register, X.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the LOW-to-
HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port B and can be
asynchronous or coincident to CLKA. EFB, FFB, AFB, and AEB are synchronized to the LOW-to-
HIGH transition of CLKB.
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
The A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is LOW, FIFO2 is empty,
when EFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory.
EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is LOW, the FIFO1 is
register when EFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the
second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is LOW, FIFO1 is full,
HIGH by the second LOW-to-HIGH transition of CLKA after reset.
FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is LOW, FIFO2 is full,
HIGH by the second LOW-to-HIGH transition of CLKB after reset.
The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which selects one of four
preset values for the Almost-Full flag and Almost-Empty flag.
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the
A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output,
and a LOW level selects FIFO2 output register data for output.
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output,
and a LOW level selects FIFO1 output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-
HIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH
when the device is reset.
4
Description
COMMERCIAL TEMPERATURE RANGE
FEBRUARY 12, 2009