ADP3208 ON Semiconductor, ADP3208 Datasheet - Page 27

• Manufacturer Part Number: ADP3208
• Description: 7-bit, Programmable, Dual-phase, Mobile, Cpu, Synchronous Buck Controller
• Manufacturer: ON Semiconductor

APPLICATION INFORMATION
The design parameters for a typical IMVP-6+-compliant CPU
core VR application are as follows:
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SETTING THE CLOCK FREQUENCY FOR PWM
In PWM operation, the ADP3208 uses a fixed-frequency control
architecture. The frequency is set by an external timing resistor
(RT). The clock frequency and the number of phases determine
the switching frequency per phase, which relates directly to the
switching losses and the sizes of the inductors and input and
output capacitors. For a dual-phase design, a clock frequency
of 600 kHz sets the switching frequency to 300 kHz per phase.
This selection represents the trade-off between the switching
losses and the minimum sizes of the output filter components.
To achieve a 600 kHz oscillator frequency at a VID voltage of
1.5 V, RT must be 250 kΩ. Alternatively, the value for RT can
be calculated by using the following equation:
where:
7.2 pF and 35 kΩ are internal IC component values.
V
n is the number of phases.
f
For good initial accuracy and frequency stability, it is
recommended to use a 1% resistor.
SETTING THE SWITCHING FREQUENCY FOR
RPM OPERATION OF PHASE 1
During the RPM operation of Phase 1, the ADP3208 runs in
pseudoconstant frequency if the load current is high enough for
continuous current mode. While in DCM, the switching
frequency is reduced with the load current in a linear manner.
SW
VID
is the switching frequency in hertz for each phase.
Maximum input voltage (V
Minimum input voltage (V
Output voltage by VID setting (V
Maximum output current (I
Droop resistance (R
Nominal output voltage at 40 A load (V
Static output voltage drop from no load to full load
(ΔV) = V
Maximum output current step (ΔI
Number of phases (n) = 2
Switching frequency per phase (f
Duty cycle at maximum input voltage (D
Duty cycle at minimum input voltage (D
is the VID voltage in volts.
RT
=
2
×
ONL
n
V
×
VID
− V
f
SW
+
1
OFL
×
0 .
7
O
= 1.4375 V − 1.3535 V = 84 mV
V
2 .
) = 2.1 mΩ
pF
−
INMIN
INMAX
O
35
) = 40 A
kΩ
) = 8 V
) = 19 V
SW
VID
O
) = 300 kHz
) = 27.9 A
) = 1.4375 V
OFL
MIN
MAX
) = 1.3535 V
) = 0.076 V
) = 0.18 V
Rev. 1 | Page 27 of 38 | www.onsemi.com
(1)
To save power with light loads, lower switching frequency is
usually preferred during RPM operation. However, the V
ripple specification of IMVP-6+ sets a limitation for the lowest
switching frequency. Therefore, depending on the inductor and
output capacitors, the switching frequency in RPM can be equal
to, greater than, or less than its counterpart in PWM.
A resistor between the VRPM and RPM pins sets the pseudo-
constant frequency as follows:
where:
A
C
R
ramp magnitude (see the Ramp Resistor Selection section for
information about the design of R
If R
switching frequency in RPM operation.
SOFT START AND CURRENT LIMIT
LATCH-OFF DELAY TIMES
The soft start and current limit latch-off delay functions share
the SS pin; consequently, these parameters must be considered
together. First, set C
generated with an 8 μA internal current source. The value for
C
where:
V
as 1.2 V.
t
to be less than 3 ms.
Therefore, assuming a desired soft start time of 2 ms, C
and the closest standard capacitance is 12 nF.
After C
by using the following equation:
where C
SS
R
R
R
SS
BOOT
is the desired soft start time and is recommended in IMVP-6+
is an external resistor on the RAMP pin to set the internal
is the internal ramp amplifier gain.
is the internal ramp capacitor value.
R
can be calculated as
= 280 kΩ, the following resistance results in 300 kHz
C
t
R
R
is the boot voltage for the CPU and is defined in IMVP-6+
DELAY
RPM
RPM
SS
SS
SS
=
is set, the current limit latch-off time can be calculated
is 7.2 ms.
=
=
8
=
μA
V
(
. 1
1
V
BOOT
2 .
4375
VID
4
×
4
V
2
×
t
×
μA
SS
+
×
237
RT
SS
V
1
C
0 .
for the soft start ramp. This ramp is
SS
+
k
V
1
Ω
0 .
)
×
V
A
×
R
R
280
0
×
R
2 .
R
1 (
×
resistance).
×
C
−
kΩ
1 (
R
D
×
−
×
)
×
f
. 0
5
V
SW
076
pF
VID
×
)
300
×
. 1
ADP3208
4375
kHz
SS
is 13.3 nF,
CORE
=
246
(2)
(3)
(4)
k
Ω