ADP3208 ON Semiconductor, ADP3208 Datasheet - Page 33

• Manufacturer Part Number: ADP3208
• Description: 7-bit, Programmable, Dual-phase, Mobile, Cpu, Synchronous Buck Controller
• Manufacturer: ON Semiconductor

POWER MONITOR
The PMON duty cycle is proportional to the load current. R
sets the maximum duty cycle at the maximum current.
where I
duty cycle, and R
When PMON is connected with a pull-up resistor to the output
voltage, as shown in Figure 38, the average PMON voltage is
given by
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3208 allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and that is equal to the droop
resistance (R
voltage droops in proportion with the load current at any load
current slew rate, ensuring the optimal position and allowing
the minimization of the output decoupling.
With the multimode feedback structure of the ADP3208, it is
necessary to set the feedback compensation so that the
converter’s output impedance works in parallel with the output
decoupling. In addition, it is necessary to compensate for the
several poles and zeros created by the output inductor and
decoupling capacitors (output filter).
A Type III compensator on the voltage feedback is adequate
for proper compensation of the output filter. Figure 41 shows the
Type III amplifier used in the ADP3208. Figure 42 shows the
locations of the two poles and two zeros created by this amplifier.
R
PMON
PMONFS
LOAD
is the load current in amps when PMON is 100%
O
=
). With the resistive output impedance, the output
=
(
(
V
R
7
I
O
GFX
LOAD
MONFS
VOLTAGE ERROR
Figure 41. Voltage Error Amplifier
COMP
is the droop resistance in ohms.
R
AMPLIFIER
A
×
×
C
I
10
×
B
R
LOAD
10
O
μA
C
A
×
μA
9 +
×
)
R
6
)
O
−
FB
1
×
1
R
C
V
9
REFERENCE
FB
V
FB
VOLTAGE
ADP3208
VOLTAGE
OUTPUT
Rev. 1 | Page 33 of 38 | www.onsemi.com
PMONFS
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The following equations give the locations of the poles and
zeros shown in Figure 42:
The expressions that follow compute the time constants for
the poles and zeros in the system and are intended to yield an
optimal starting point for the design; some adjustments may be
necessary to account for PCB and component parasitic effects
(see the Tuning Procedure for ADP3208 section):
where:
R' is the PCB resistance from the bulk capacitors to the ceramics
and is approximately 0.4 mΩ (assuming an 8-layer motherboard).
R
A
V
L
X
DS
D
RT
is 150 pH for the six Panasonic SP capacitors.
is 5.
is the total low-side MOSFET for on resistance per phase.
is 1.25 V.
T
T
T
T
R
f
f
f
f
C
B
D
Z1
Z2
P1
P2
A
E
GAIN
=
=
=
=
=
=
=
=
=
2
(
Figure 42. Poles and Zeros of Voltage Error Amplifier
C
V
n
C
R
π 2
2
π 2
π 2
×
RT
×
X
0dB
( π
X
X
n
L
R
×
×
×
×
×
×
C
+
×
–20dB/DEC
×
O
(
C
C
C
R
C
(
R
R
⎛
⎜
⎜
⎝
C
A
1 (
V
R
1
+
L
A
FB
A
A
X
O
'
f
1
VID
X
+
−
P1
O
−
×
×
A
−
×
+
1
−
R
C
×
×
(
−
R
C
D
n
C
O
×
R
R
A
C
R
B
R
2
A
B
×
×
O
)
R
)
B
'
D
FB
Z
)
×
×
'
×
×
D
)
E
R
×
+
×
×
C
+
R
C
f
DS
))
V
L
R
R
SW
R
C
X
f
FB
A
VID
Z2
×
X
O
DS
O
2
Z
+
V
×
×
⎞
⎟
⎟
⎠
R
RT
f
R
R
Z1
L
V
O
O
×
R
–20dB/DEC
VID
V
−
X
f
R
P2
RT
'
+
FREQUENCY
ADP3208
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)