ADP3208 ON Semiconductor, ADP3208 Datasheet - Page 9

• Manufacturer Part Number: ADP3208
• Description: 7-bit, Programmable, Dual-phase, Mobile, Cpu, Synchronous Buck Controller
• Manufacturer: ON Semiconductor

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
EN
PWRGD
PGDELAY
CLKEN
FBRTN
FB
COMP
SS
ST
VARFREQ
VRTT
TTSNS
PMON
PMONFS
Description
Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD
and VRTT low, and pulls CLKEN high.
Power-Good Output. Open-drain output. A low logic state means that the output voltage is outside
of the VID DAC defined range.
Power-Good Delay Setting Input/Output. A capacitor connected from this pin to GND sets the
power-good delay time.
Clock Enable Output. Open-drain output. A low logic state enables the CPU internal PLL clock to
lock to the external clock.
Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the
ground return for the VID DAC and the voltage error amplifier blocks.
Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
Voltage Error Amplifier Output and Frequency Compensation Point.
Soft Start and Latch-Off Delay Setting Input/Output. An external capacitor from this pin to GND sets
the soft start ramp-up time and the current limit latch-off delay ramp-down time.
Soft Transient Slew Rate Timing Input/Output. A capacitor from this pin to GND sets the slew rate of
the output voltage when it transitions from one VID setting to another, including boot-to-active
VID, VID on the fly, and deeper sleep entry and exit transients.
Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with
VID code.
Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator
temperature at the remote sensing point exceeded a set alarm threshold level.
Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is
connected to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is
connected to this pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables
the thermal throttling function and disables the crowbar, or overvoltage protection (OVP), feature
of the chip.
Power Monitor Output. Open-drain output. A pull-up resistor from PMON to CSREF provides a duty
cycle–modulated power output signal. An external RC network can be used to convert the digital
signal stream to an averaged power analog output voltage.
Power Monitor Full-Scale Setting Input/Output. A resistor from this pin to GND sets the full-scale
value of the PMON output signal.
PGDELAY
VARFREQ
PWRGD
CLKEN
FBRTN
TTSNS
COMP
VRTT
EN
FB
SS
ST
10
11
12
1
2
3
4
5
6
7
8
9
Rev. 1 | Page 9 of 38 | www.onsemi.com
Figure 3. LFCSP Pin Configuration
PIN 1
INDICATOR
(Not to Scale)
ADP3208
TOP VIEW
36
35
34
33
32
31
30
29
28
27
26
25
BST1
DRVH1
SW1
PVCC1
DRVL1
PGND1
PGND2
DRVL2
PVCC2
SW2
DRVH2
BST2
ADP3208