SPC8106F0C EPSON Research and Development, Inc., SPC8106F0C Datasheet - Page 10

• Manufacturer Part Number: SPC8106F0C
• Description: VGA LCD CONTROLLER
• Manufacturer: EPSON Research and Development, Inc.

Key
CPU Interface
A
I
O
Pin Name
A[0:16],
LA[17:23]
ALE
D[0:15]
MEMEN
IOR#
IOW#
MEMR#
MEMW#
IOEN#
READY
RESET
IRQ
MEMCS16# O
10
SPC8106F0C
PIN DESCRIPTION
= Analog
= Input
= Output
GRAPHICS
Type Pin #
I
I
I/O
I
I
I
I
I
I
O
I
O
104..107,
110..122,
2..4, 5..8
102
125..140
97
94
95
96
98
93
142
141
103
99
I/O = Bidirectional
P
= Power
Description
CPU bus address inputs. In Suspend Mode, the Address inputs are internally
masked off. If the value on MD[5] at RESET = 1, then the ALE input pin is used to
internally latch LA[19:17] and A[16:2], allowing these address bits to be driven by
the processor address bus. If the value on MD[5] at RESET = 0, then standard ISA
address timing is assumed, where pins A[0:16], LA[17:23] should be connected to
the ISA bus signals SA[0:16], LA[17:23] respectively.
ISA Bus Address Latch Enable. In Suspend Mode the ALE input is disabled. If the
value on MD[5] at RESET = 1, then the ALE input is used to internally latch
LA[19:17] and A[16:2], allowing these address bits to be driven by the processor
address bus. In this mode, the processor ADS# output should be connected to this
pin. If the value on MD[5] at RESET = 0, then standard ISA address timing is
assumed, and only the LA[19:17] inputs are internally latched.
16 bit ISA-Bus data bus. These lines are driven by the chip only during read cycles,
and are in a hi-Z state at all other times. In Suspend Mode, these inputs are
internally masked off.
ISA Bus Memory Enable. This signal should be connected to the REFRESH# signal
on the ISA bus. When this signal is low (e.g. during a system memory refresh
cycle), memory address decoding is disabled.
ISA Bus I/O Read Strobe. In Suspend Mode the IOR# input is disabled.
ISA Bus I/O Write Strobe. In Suspend Mode the IOW# input is disabled.
ISA Bus System Memory Read Strobe. In Suspend Mode the MEMR# input is
disabled.
ISA Bus System Memory Write Strobe. In Suspend Mode the MEMW# input is
disabled.
ISA Bus I/O Enable. This input should be connected to the ISA bus AEN signal.
When this signal is high, I/O address decoding is disabled. In Suspend Mode, the
IOEN# input is disabled.
ISA Bus READY signal. This output is driven low to force the CPU to insert wait
states during memory cycles. READY is released to high-Z after a transfer is
complete.
The active high Reset signal from the CPU clears all internal registers and forces all
signals to their inactive state.
ISA Bus Vertical Interrupt. When enabled, a Vertical Retrace Interrupt will cause
this signal to be driven from a logic 0 state to a logic 1 (rising-edge triggered
interrupt). Once set, this interrupt must be cleared by a bit in the CRTC registers. A
control bit in the Auxiliary Registers allows this output to be optionally disabled (tri-
stated). This pin also is used for the output of the NAND tree in pin test mode.
ISA Bus Memory Chip Select 16. Address inputs LA[23:17] are decoded to drive
this output low when a valid memory address (AXXXXh, BXXXXH) appears on the
bus.
X12-DS-001-09