SPC8106F0C EPSON Research and Development, Inc., SPC8106F0C Datasheet - Page 6

• Manufacturer Part Number: SPC8106F0C
• Description: VGA LCD CONTROLLER
• Manufacturer: EPSON Research and Development, Inc.

The Sequencer
CRT Controller
CRT Interface
Address Generator
Attributes Controller
Graphics Controller
Display Memory Interface
Memory Decoder
SPC8106F0C
FUNCTIONAL BLOCK DESCRIPTION
The Sequencer generates internal signals to syn-
chronize the operation of the chip as well as the sig-
nals to control the timing of the display DRAM. The
Sequencer also arbitrates between CPU and video
display accesses to the DRAM. It contains registers
that allow the selection of the character font set, con-
trol the structure of the video memory and allow write
masking of the individual plane of memory.
The CRT Controller generates the horizontal and ver-
tical synchronization signals for the CRT, single panel
or dual panel LCD display and character and/or pixel
addresses for display data from DRAM.
The CRT Interface aligns CRT signals to the Pixel
Clock and generates the I/O Control signals for CPU
access to the RAMDAC.
The Address Generator takes the display and refresh
addresses from the CRT Controller and converts
them into RAS and CAS addresses for the display
DRAM, and multiplexes these display accesses with
CPU memory accesses.
The Attributes Controller takes in pixel and attribute
information from the Graphics Controller and display
DRAM and formats the data into pixel information
which then passes through the lookup table. It also
controls display character attributes such as blink,
underline and horizontal pixel panning.
The Graphics Controller supplies display memory
data to the Attributes Controller during display time
and provides data translation between the CPU bus
and the display memory during CPU read or write
access cycles.
The Display Memory Interface is a bridge by which
the chip communicates with the DRAM. It contains
buffers that are used to store recently fetched DRAM
data.
The Memory Decoder monitors the CPU-bus activity
and decodes cycles for the display DRAM. It supplies
memory access control signals to the Sequencer.
6
GRAPHICS
Port Decoder
Auxiliary Ports
VGA Ports
Clock Generation
Power Save
Lookup Table
LCD Interface
Hardware Cursor
The Port Decoder decodes CPU-bus I/O cycles to
provide enable and write strobes for the on-chip I/O
registers.
The Auxiliary Ports are I/O registers used to control
functions of the chip beyond the basic VGA register
set. Registers are included for controlling the LCD
interface circuits as well as the power save modes.
The VGA Ports contain the Miscellaneous Output
Status register and the Video Subsystem Enable reg-
ister used in VGA mode.
The Clock Generation contains oscillator support for
external crystals.
Power Save contains the logic to implement six soft-
ware controlled and one hardware controlled power
down modes.
The Lookup Table consists of a memory array of 256
locations of 12 bits each and hardware to convert
VGA palette writes to gray-scale values.
The LCD Interface converts the display video data
from the Lookup Table into LCD display data. It also
generates control signals necessary to drive single or
dual-panel LCD panels. For monochrome LCD pan-
els, the LCD Interface generates a maximum 64 gray
shades through frame rate modulation and dithering
techniques. For color LCD panels, the LCD Interface
generates 256 simultaneous colors from a possible
4096 colors through frame rate modulation.
The Hardware Cursor generates a 4 gray shade or
color cursor/sprite that can be overlaid on the LCD or
CRT display. The cursor is 64 x 64 pixels or optionally
expanded to 128 x 128 through pixel replication.
X12-DS-001-09