SPC8106F0C EPSON Research and Development, Inc., SPC8106F0C Datasheet - Page 13

• Manufacturer Part Number: SPC8106F0C
• Description: VGA LCD CONTROLLER
• Manufacturer: EPSON Research and Development, Inc.

External CRT/RAMDAC Interface
X12-DS-001-09
Pin Name
P[0:7]
PCLK
BLANK#
HSYNC#
VSYNC#
DACRD#
DACWR#
RS2
OL[0:1]
OL23
D477
IREFEN#
Type
O
O
O
O
O
O
O
O
I/O
O
O
O
Pin #
26..33
34
44
41
42
43
45
46
39, 38
35
40
47
Pixel Clock. Pixel data is clocked out of the chip on the falling edge of PCLK.
Description
When MD[7]=1 at RESET, these pins are the Pixel Data outputs. These 8 bits are
connected to the pixel select inputs of the external RAMDAC.
Blank output. This output is clocked out on the falling edge of PCLK and is driven
low during display blanking periods.
Horizontal Sync. This output is clocked out on the falling edge of PCLK and is
driven to indicate the horizontal retrace period. The polarity of this signal is
determined by a control bit in register 3C2h.
Vertical Sync. This output is clocked out on the falling edge of PCLK and is driven
to indicate the vertical retrace period. The polarity of this signal is determined by a
control bit in register 3C2h.
RAMDAC Read Strobe. This signal goes low when a valid read access to the VGA
RAMDAC is decoded by the chip.
RAMDAC Write Strobe. This signal goes low when a valid write access to the VGA
RAMDAC is decoded by the chip.
Register Select 2 output. This output should be connected to the RS2 input of the
RAMDAC (Bt477 or equivalent). The logic level on this output may be set by
setting Auxiliary Register [0B] bit 3. This signal is required to allow CPU access the
control and overlay registers of the external RAMDAC.
Multiple Function:
Overlay Select outputs 1:0
When MD[13]=0 at RESET, these pins are outputs used to provide sprite/HW
cursor function on the CRT display. In this case, these outputs should be
connected to the OL[0:1] inputs of the RAMDAC (Bt477 or equivalent). They are
used by the sprite circuitry to access the overlay registers in the RAMDAC. For
alternate function see “Multiple Function Pin Descriptions” on page 16.
Overlay Select output 2/3. This output should be connected to both the OL2 and
OL3 inputs of the RAMDAC (Bt477 or equivalent). This signal is used by the sprite
circuitry to access the overlay registers in the RAMDAC. For alternate function see
“Multiple Function Pin Descriptions” on page 16.
477 Control Signal. This output should be connected to the 477/471 input of the
RAMDAC (Bt477 or equivalent). This signal is used to access the control register
of the RAMDAC and to allow it to be powered down. The logic level on this output
can be controlled by setting Auxiliary Register [0B] bit 4, and is also controlled by
the power save logic.
IREF Enable output. This signal is used to control the external current reference
source required by the RAMDAC, allowing powering down the analog circuitry
when not required. When this signal is driven low, the external current reference
should be enabled. When this signal is high, the external current reference should
be shut off.
SPC8106F0C
GRAPHICS
13