SPC8106F0C EPSON Research and Development, Inc., SPC8106F0C Datasheet - Page 14

• Manufacturer Part Number: SPC8106F0C
• Description: VGA LCD CONTROLLER
• Manufacturer: EPSON Research and Development, Inc.

Power Save Mode Control
Power Supply
Pin Name
MS[2:0]
Pin Name
SUSPEND# I
PDCLK
Pin Name
COREVDD
IOVDD
VSS
IOVSS
14
SPC8106F0C
GRAPHICS
Type
I/O
Type
I
Type Pin #
P
P
P
P
14, 37,
85, 92,
109
1, 50, 73,
124
11, 36,
88, 89,
108
49, 72,
123, 144
Pin #
83, 82, 71
Pin #
84
143
Description
V DD supply for core logic.
V DD supply for interface pins.
V SS supply for core logic.
V SS supply for interface pins.
Description
Monitor Sense inputs. These signals should be connected to the monitor sense
lines from the CRT monitor cable. The status of these bits is readable in Auxiliary
Register [08] bits 2:0, and is used by BIOS software to determine the presence
and type of monitor connected. Optionally, the SENSE output of the RAMDAC
may be connected to one of these inputs to allow the BIOS to read the SENSE
signal and detect the monitor. MS[2:1] can be forced low by the DCC2 monitor
support bits in Auxiliary Register [10] bits 1:0.
Description
A low level on this pin puts the chip into a hardware power down mode. The
SUSPEND# signal overrides any software initiated power down modes, and
disables the ISA-Bus interface inputs except RESET. Address and Data inputs are
also masked when this signal is low. When in Suspend Mode the UD(3:0), LD(3:0),
XSCL, XSCL2, LP, YD and WF signals are driven into a high impedance or low
state (configurable) and the LCDPWR# signal is driven high.
Power Down Clock. This input may be used to provide a low frequency clock for
generating refresh in Power Save Modes 4 and Suspend, as an optional
alternative to using the pixel clock or MEMEN input as the refresh clock source.
This clock input should be driven by either by a 32 kHz 50% duty cycle clock
source, or a 64 kHz clock source with a high period as short as possible (but >
minimum RAS low pulse width) to minimize DRAM current consumption during
refresh. The PDCLK input is used to directly generate the RAS and CAS pulses
during Power Save Mode 4 and Suspend.
X12-DS-001-09