LM3S1150 Luminary Micro, Inc, LM3S1150 Datasheet - Page 14

• Manufacturer Part Number: LM3S1150
• Description: Lm3s1150 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Register 32:
General-Purpose Timers ............................................................................................................. 205
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Watchdog Timer ........................................................................................................................... 241
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 264
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
14
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 204
GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 217
GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 218
GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 220
GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 222
GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 225
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 227
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 228
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 229
GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 231
GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 232
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 233
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 234
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 235
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 236
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 237
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 238
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 239
GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 240
Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 244
Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 245
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 246
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 247
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 248
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 249
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 250
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 251
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 252
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 253
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 254
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 255
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 256
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 257
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 258
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 259
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 260
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 261
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 262
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 263
UART Data (UARTDR), offset 0x000 ............................................................................... 272
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 274
UART Flag (UARTFR), offset 0x018 ................................................................................ 276
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 278
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 279
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 280
Preliminary
July 26, 2008