LM3S1150 Luminary Micro, Inc, LM3S1150 Datasheet - Page 456

• Manufacturer Part Number: LM3S1150
• Description: Lm3s1150 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Signal Tables
456
QEI
SSI
System Control &
Clocks
UART
Function
VDD25
VDD25
VDD25
VDD25
VDDA
VDDA
WAKE
IDX0
PhA0
PhB0
SSI0Clk
SSI0Fss
SSI0Rx
SSI0Tx
SSI1Clk
SSI1Fss
SSI1Rx
SSI1Tx
CMOD0
CMOD1
OSC0
OSC1
RST
TRST
XOSC0
XOSC1
U0Rx
Pin Name
Number
100
Pin
14
38
62
88
98
50
47
28
29
30
31
72
73
74
75
65
76
48
49
64
89
52
53
26
11
3
Preliminary
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
-
-
-
-
-
-
I
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Buffer
Power
Power
Power
Power
Power
Power
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
-
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for most of the logic function,
including the processor core and most peripherals.
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
An external input that brings the processor out of
hibernate mode when asserted.
QEI module 0 index
QEI module 0 Phase A
QEI module 1 Phase B
SSI module 0 clock
SSI module 0 frame
SSI module 0 receive
SSI module 0 transmit
SSI module 1 clock
SSI module 1 frame
SSI module 1 receive
SSI module 1 transmit
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
Main oscillator crystal input or an external clock
reference input.
Main oscillator crystal output.
System reset input.
JTAG TRSTn
Hibernation Module oscillator crystal input or an
external clock reference input. Note that this is
either a 4.19-MHz crystal or a 32.768-kHz oscillator
for the Hibernation Module RTC. See the CLKSEL
bit in the HIBCTL register.
Hibernation Module oscillator crystal output.
UART module 0 receive. When in IrDA mode, this
signal has IrDA modulation.
Description
July 26, 2008