LM3S1439 Luminary Micro, Inc, LM3S1439 Datasheet - Page 298
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LM3S1439
Manufacturer Part Number
LM3S1439
Description
Lm3s1439 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1439.pdf
(544 pages)
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Universal Asynchronous Receivers/Transmitters (UARTs)
13.1
13.2
13.2.1
298
Block Diagram
Figure 13-1. UART Module Block Diagram
Functional Description
Each Stellaris
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 316). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected
to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit, and followed by the data
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 13-2 on page 299 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
System Clock
Interrupt
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
Identification
Registers
®
UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
Preliminary
Interrupt Control
UARTRSR/ECR
Control/Status
UARTLCRH
UARTILPR
UARTIFLS
UARTMIS
UARTICR
UARTCTL
UARTRIS
UARTDR
UARTFR
UARTIM
UARTFBRD
Baud Rate
UARTIBRD
Generator
TxFIFO
RxFIFO
16 x 8
16 x 8
.
.
.
.
.
.
Transmitter
Receiver
(with SIR
Encoder)
(with SIR
Decoder)
Transmit
Receive
July 25, 2008
UnTx
UnRx
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