LM3S317 Luminary Micro, Inc, LM3S317 Datasheet - Page 200
LM3S317
Manufacturer Part Number
LM3S317
Description
Lm3s317 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S317.pdf
(376 pages)
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Analog-to-Digital Converter (ADC)
11.1
11.2
11.2.1
200
Block Diagram
Figure 11-1. ADC Module Block Diagram
Functional Description
The Stellaris ADC collects sample data by using a programmable sequence-based approach
instead of the traditional single or double-sampling approach found on many ADC modules. Each
sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing
the ADC to collect data from multiple input sources without having to be re-configured or serviced
by the controller. The programming of each sample in the sample sequence includes parameters
such as the input source and mode (differential versus single-ended input), interrupt generation on
sample completion, and the indicator for the last sample in the sequence.
Sample Sequencers
The sampling control and data capture is handled by the Sample Sequencers. All of the
sequencers are identical in implementation except for the number of samples that can be captured
and the depth of the FIFO. Table 11-1 shows the maximum number of samples that each
Sequencer can capture and its corresponding FIFO depth. In this implementation, each FIFO entry
is a 32-bit word, with the lower 10 bits containing the conversion result.
Table 11-1. Samples and FIFO Depth of Sequencers
SS0 Interrupt
SS1 Interrupt
SS2 Interrupt
SS3 Interrupt
GPIO (PB4)
GPIO (PB4)
GPIO (PB4)
GPIO (PB4)
Comparator
Comparator
Comparator
Comparator
Sequencer
Timer
PWM
Timer
PWM
Timer
PWM
Timer
PWM
SS3
SS2
SS1
SS0
Trigger Events
ADCEMUX
ADCPSSI
SS3
SS2
SS1
SS0
Number of
Samples
1
4
4
8
Interrupt Control
Control / Status
ADCACTSS
ADCOSTAT
ADCUSTAT
ADCSSPRI
ADCRIS
ADCISC
ADCIM
Depth of FIFO
Preliminary
1
4
4
8
ADCSSFSTAT0
ADCSSFSTAT1
ADCSSFSTAT2
ADCSSFSTAT3
ADCSSMUX0
ADCSSMUX1
ADCSSMUX2
ADCSSMUX3
ADCSSCTL0
ADCSSCTL1
ADCSSCTL2
ADCSSCTL3
Sequencer 0
Sequencer 1
Sequencer 2
Sequencer 3
Sample
Sample
Sample
Sample
Hardware Averager
Analog-to-Digital
ADCSSFIFO0
ADCSSFIFO1
ADCSSFIFO2
ADCSSFIFO3
FIFO Block
Converter
ADCSAC
February 6, 2007
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