LM3S317 Luminary Micro, Inc, LM3S317 Datasheet - Page 74
![no-image](/images/no-image-200.jpg)
LM3S317
Manufacturer Part Number
LM3S317
Description
Lm3s317 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S317.pdf
(376 pages)
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System Control
74
Reset
Reset
Type
Type
Bit/Field
31:7
Interrupt Mask Control (IMC)
Offset 0x054
6
5
4
3
2
RO
RO
31
15
0
0
Register 14: Interrupt Mask Control (IMC), offset 0x054
Central location for system control interrupt masks.
RO
RO
30
14
0
0
reserved
PLLLIM
MOFIM
LDOIM
IOFIM
Name
CLIM
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
Reset
RO
RO
25
0
9
0
0
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
PLL Lock Interrupt Mask
This bit specifies whether a current limit detection is
promoted to a controller interrupt. If set, an interrupt is
generated if PLLLRIS in RIS is set; otherwise, an interrupt
is not generated.
Current Limit Interrupt Mask
This bit specifies whether a current limit detection is
promoted to a controller interrupt. If set, an interrupt is
generated if CLRIS is set; otherwise, an interrupt is not
generated.
Internal Oscillator Fault Interrupt Mask
This bit specifies whether an internal oscillator fault
detection is promoted to a controller interrupt. If set, an
interrupt is generated if IOFRIS is set; otherwise, an
interrupt is not generated.
Main Oscillator Fault Interrupt Mask
This bit specifies whether a main oscillator fault detection is
promoted to a controller interrupt. If set, an interrupt is
generated if MOFRIS is set; otherwise, an interrupt is not
generated.
LDO Power Unregulated Interrupt Mask
This bit specifies whether an LDO unregulated power
situation is promoted to a controller interrupt. If set, an
interrupt is generated if LDORIS is set; otherwise, an
interrupt is not generated.
RO
RO
23
0
7
0
PLLLIM
R/W
RO
22
0
6
0
CLIM
R/W
RO
21
0
5
0
IOFIM MOFIM LDOIM BORIM PLLFIM
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
February 6, 2007
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
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