MT18VDDT3272 Micron, MT18VDDT3272 Datasheet - Page 14

• Manufacturer Part Number: MT18VDDT3272
• Description: 184-Pin Registered DDR SDRAM DIMMs (x72)
• Manufacturer: Micron

32, 64 Meg x 72 DDR SDRAM DIMMs
DD18C32_64X72AG_B.p65–Rev. B, Pub. 1/02
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1–5, 12–15, 31; notes appear following parameter tables)
(0°C
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to V
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
T
A
+70°C; V
DD
Q = +2.5V ±0.2V, V
DD
CL = 2.5
CL = 2
DD
= +2.5V ±0.2V)
SYMBOL MIN
t
t
t
CK (2.5)
t
DQSCK
t
t
t
t
WPRES
t
t
t
t
t
t
t
t
t
CK (2)
DQSQ
t
DQSH
t
WPRE
WPST
DIPW
DQSL
DQSS
t
t
t
t
t
t
t
XSNR
XSRD
t
t
RPRE
MRD
RPST
t
WTR
REFC
t
t
t
t
DSH
t
t
QHS
RCD
RRD
REFI
VTD
t
t
t
RAS
RAP
t
t
t
DSS
t
t
t
RFC
QH
WR
na
AC
CH
DH
DS
HP
HZ
IH
IH
RC
CL
RP
LZ
IS
IS
F
S
F
S
14
t
CH,
-0.75
-0.75
-0.45
-0.75
0.45
1.75
0.35
0.35
0.75
0.25
200
7.5
7.5
0.5
0.5
0.2
0.2
.90
.90
0.9
0.4
0.4
15
40
65
75
20
20
15
15
t
75
1
1
0
1
QH -
0
t
HP -
t
CL
-26A
t
t
120,000
DQSQ
QHS
+0.75
MAX
+0.75
+0.55
+0.75
140.6
0.55
1.25
0.75
15.6
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0.5
1.1
0.6
0.6
13
13
RAS(MIN) - (burst length *
184-pin DDR SDRAM DIMMs
t
CH,
256MB, 512MB (ECC x72)
-0.75
-0.75
-0.75
MIN
0.45
0.45
1.75
0.35
0.35
0.75
0.25
t
200
7.5
0.5
0.5
0.2
0.2
.90
.90
0.9
0.4
0.4
10
15
40
65
75
20
20
15
15
QH -
75
1
1
0
1
0
t
HP -
t
CL
-265
t
120,000
t
DQSQ
QHS
+0.75
+0.75
+0.75
MAX
140.6
0.55
0.55
1.25
0.75
15.6
0.5
1.1
0.6
0.6
13
13
t
CH,
MIN
0.45
0.45
0.35
0.35
0.75
0.25
-0.8
-0.8
-0.8
t
200
0.6
0.6
0.2
0.2
1.1
1.1
1.1
1.1
0.9
0.4
0.4
40
t
10
16
70
80
20
20
15
15
80
CK/2)
QH -
8
2
0
1
0
t
t
HP-
CL
-202
t
t
120,000
QHS
DQSQ
MAX
140.6
+0.8
+0.8
+0.8
0.55
0.55
1.25
15.6
0.6
1.1
0.6
0.6
13
13
1
©2002, Micron Technology, Inc.
UNITS NOTES
t
t
t
t
t
t
t
t
t
t
t
t
t
ns
CK
CK
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
ns
CK
ns
CK
ns
µs
µs
ns
ns
CK
40, 47, 48
40, 47
23, 27
23, 27
22, 25
16, 37
16, 38
22, 23
18, 19
22
12
12
12
12
26
26
27
30
31
41
45
37
17
21
21