MT18VDDT3272 Micron, MT18VDDT3272 Datasheet - Page 16

• Manufacturer Part Number: MT18VDDT3272
• Description: 184-Pin Registered DDR SDRAM DIMMs (x72)
• Manufacturer: Micron

32, 64 Meg x 72 DDR SDRAM DIMMs
DD18C32_64X72AG_B.p65–Rev. B, Pub. 1/02
NOTES
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. I
All voltages referenced to V
Tests for AC timing, I
characteristics may be conducted at nominal
reference/supply voltage levels, but the related
specifications and device operation are guaran-
teed for the full voltage range specified.
Outputs measured with equivalent load:
AC timing and I
of up to 1.5V in the test environment, but input
timing is still referenced to V
point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew
rate for the input signals used to test the device is
1V/ns in the range between V
The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back above
[below] the DC input LOW [HIGH] level).
V
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V
DC value. Thus, from V
±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V
V
system supply for signal termination resistors, is
expected to be set equal to V
variations in the DC level of V
I
Specified values are obtained with minimum cycle
time at CL = 2 for -26A and -202, CL = 2.5 for -265
with the outputs open.
Enables on-chip refresh and address counters.
properly initialized, and is averaged at the defined
cycle rate.
DD
DD
REF
TT
is dependent on output loading and cycle rates.
specifications are tested after the device is
is not applied directly to the device. V
is expected to equal V
REF
Output
(V
REF
by-pass capacitor.
OUT
may not exceed ±2 percent of the
DD
)
tests may use a V
DD
V
, and electrical AC and DC
TT
DD
50
30pF
Reference
Point
Q/2, V
DD
SS
REF
REF
.
Q/2 of the transmit-
IL
REF
(
AC
and must track
(or to the crossing
REF
.
) and V
IL
is allowed
-to-V
IH
TT
IH
(
AC
swing
is a
).
16
11. This parameter is sampled. V
12. Command/Address input slew rate = 0.5V/ns. For -
13. The CK/CK# input reference level (for timing
14. Inputs are not recognized as valid until V
15. The output timing reference level, as measured at
16.
17. The maximum limit for this parameter is not a
18. This is not a device limit. The device will operate
19. It is recommended that DQS be valid (HIGH or
20. MIN (
= +2.5V ±0.2V, V
V
input is grouped with I/O pins, reflecting the fact
that they are matched in loading.
265 with slew rates 1V/ns and faster,
reduced to 900ps. If the slew rate is less than 0.5V/
ns, timing must be derated:
50ps per each 100mV/ns reduction in slew rate
from the 500mV/ns.
remains constant. If the slew rate exceeds 4.5V/ns,
functionality is uncertain.
referenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V
stabilizes. Exception: during the period before V
stabilizes, CKE 0.3 x V
the timing reference point indicated in Note 3, is
V
t
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
device limit. The device will operate with a greater
value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
with a negative value, but system performance
could be degraded due to bus turnaround.
LOW) on or before the WRITE command. The case
shown (DQS going from High-Z to logic LOW)
applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on
smallest multiple of
absolute value for the respective parameter.
(MAX) for I
of
t
HZ and
RAS.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
OUT
TT
t
184-pin DDR SDRAM DIMMs
CK that meets the maximum absolute value for
.
(
DC
t
RC or
) = V
256MB, 512MB (ECC x72)
t
LZ transitions occur in the same access
DD
DD
t
RFC) for I
measurements is the largest multiple
Q/2, V
t
DQSS.
REF
= V
t
OUT
t
CK that meets the minimum
IH has 0ps added, that is, it
SS
DD
REF
DD
, f = 100 MHz, T
(peak to peak) = 0.2V. DM
measurements is the
Q is recognized as LOW.
.
DD
t
IS has an additional
= +2.5V ±0.2V, V
©2002, Micron Technology, Inc.
t
IS and
A
= 25°C,
REF
t
t
IH are
RAS
DD
REF
Q