MT18VDDT3272 Micron, MT18VDDT3272 Datasheet - Page 8

• Manufacturer Part Number: MT18VDDT3272
• Description: 184-Pin Registered DDR SDRAM DIMMs (x72)
• Manufacturer: Micron

Read Latency
tween the registration of a READ command and the avail-
ability of the first bit of output data. The latency can be set
to 2 or 2.5 clocks, as shown in CAS Latency Diagram.
the latency is m clocks, the data will be available nomi-
nally coincident with clock edge n + m. The CAS Latency
Table indicates the operating frequencies at which each
CAS latency setting can be used.
eration or incompatibility with future versions may re-
sult.
32, 64 Meg x 72 DDR SDRAM DIMMs
DD18C32_64X72AG_B.p65–Rev. B, Pub. 1/02
COMMAND
COMMAND
The READ latency is the delay, in clock cycles, be-
If a READ command is registered at clock edge n, and
Reserved states should not be used as unknown op-
DQS
DQS
CK#
CK#
DQ
DQ
CK
CK
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC and nominal t DSDQ
T0
T0
CAS Latency
Diagram
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
T1
T1
T2
NOP
NOP
T2
T2n
T2n
DON’T CARE
T3
NOP
NOP
T3
T3n
T3n
8
Operating Mode
MODE REGISTER SET command with bits A7-A11 (for
the 256MB), or A7-A12 (for the 512MB module) each set to
zero, and bits A0-A6 set to the desired values. A DLL reset
is initiated by issuing a MODE REGISTER SET command
with bits A7 and A9-A11 (for 256MB module), or A7 and
A9-A12 (for 512MB module) each set to zero, bit A8 set to
one, and bits A0-A6 set to the desired values. Although
not required by the Micron device, JEDEC specifications
recommend when a LOAD MODE REGISTER command
is issued to reset the DLL, it should always be followed by
a LOAD MODE REGISTER command to select normal
operating mode.
A12 are reserved for future use and/or test modes. Test
modes and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
The normal operating mode is selected by issuing a
All other combinations of values for A7-A11, or A7-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SPEED
-26A
184-pin DDR SDRAM DIMMs
-265
-202
256MB, 512MB (ECC x72)
CAS Latency (CL)
75
75
75
Table
ALLOWABLE OPERATING
CL = 2
f
f
f
FREQUENCY (MHz)
133
100
100
©2002, Micron Technology, Inc.
75
75
75
CL = 2.5
f
f
f
133
133
125