MT18VDDT6472PHG-265 Micron, MT18VDDT6472PHG-265 Datasheet - Page 20

• Manufacturer Part Number: MT18VDDT6472PHG-265
• Description: 512MB DDR SDRAM SODIMM
• Manufacturer: Micron

pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
(256MB, 512MB, 1GB). However, an AUTO
REFRESH command must be asserted at least
once every 140.6µs (128MB) or 70.3µs (256MB,
512MB, 1GB); burst refreshing or posting by the
DRAM controller greater than eight refresh cycles
is not allowed.
other specifications:
(
in direct porportion with the clock duty cycle and
a practical data valid window can be derived, as
shown in Figure 7, Derating Data Valid Window.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyond which functionality is
uncertain. The data valid window derating curves
are provided below for duty cycles ranging
between 50/50 and 45/55.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
t
QH =
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
t
HP -
50/50
3.750
2.500
t
QHS). The data valid window derates
NA
49.5/50.5
3.700
-335 @
-262/-26A/-265 @
-262/-26A/-265 @
2.463
t
HP (
t
CK = 6ns
t
Figure 7: Derating Data Valid Window
CK/2),
3.650
49/51
2.425
t
t
CK = 10ns
CK = 7.5ns
t
RFC [MIN]) else
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
t
DQSQ, and
48.5/52.5
3.600
2.388
48/52
3.550
t
(
QH
t
2.350
QH -
Clock Duty Cycle
20
t
DQSQ)
47.5/53.5
3.500
25. To maintain a valid level, the transitioning edge of
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
2.313
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
200-PIN DDR SDRAM SODIMM
the input must:
be 1V/ns (2V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5 V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4 V/ns, functionality is uncer-
tain. For -335, slew rates must be 0.5 V/ns.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
a. Sustain a constant slew rate from the current
DH for each 100 mv/ns reduction in slew rate. If
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
maintain at least the target DC level, V
V
AC level through to the target AC level, V
or V
IH
47/53
3.450
must not vary more than 4 percent if CKE is
(
2.275
DC
IH
).
(
AC
46.5/54.5
).
3.400
2.238
3.350
46/54
©2004 Micron Technology, Inc. All rights reserved.
2.200
45.5/55.5
3.300
2.163
ADVANCE
IL
3.250
45/55
t
DS and
(
2.125
DC
IL
(
) or
AC
)