MT18VDDT6472PHG-265 Micron, MT18VDDT6472PHG-265 Datasheet - Page 9

• Manufacturer Part Number: MT18VDDT6472PHG-265
• Description: 512MB DDR SDRAM SODIMM
• Manufacturer: Micron

Table 6:
NOTE:
Table 7:
pdf: 09005aef808ffe58, source: 09005aef808ffdc7
DD9C16_32_64_128x72PHG.fm - Rev. B 9/04 EN
1. For a burst length of two, A1-Ai select the two- data-
2. For a burst length of four, A2-Ai select the four- data-
3. For a burst length of eight, A3-Ai select the eight-
4. Whenever a boundary of the block is reached within a
5. i = 9 for 128MB, 256MB
LENGTH
BURST
element block; A0 selects the first access within the
block.
element block; A0-A1 select the first access within the
block.
data-element block; A0-A2 select the first access within
the block.
given sequence above, the following access wraps
within the block.
i = 9, 11 for 512MB, 1GB
SPEED
-26A
-335
-262
-265
2
4
8
A2 A1 A0
STARTING
ADDRESS
0
0
0
0
1
1
1
1
COLUMN
Burst Definition Table
CAS Latency (CL) Table
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
75
75
75
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLOCK FREQUENCY (MHZ)
CL = 2
ALLOWABLE OPERATING
N/A
f
f
f
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
ORDER OF ACCESSES WITHIN
SEQUENTIAL
133
133
100
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
A BURST
128MB, 256MB, 512MB, 1GB (x72, ECC, PLL, SR)
75
75
75
75
INTERLEAVED
CL = 2.5
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
f
f
f
f
0-1
1-0
167
133
133
133
9
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 7,
CAS Latency (CL) Table, on page 9, indicates the oper-
ating frequencies at which each CAS latency setting
can be used.
operation or incompatibility with future versions may
result.
Operating Mode
MODE REGISTER SET command with bits A7–A11
(128MB), A7–A12 (256MB, 512MB), or A7–A13 (1GB)
each set to zero, and bits A0–A6 set to the desired val-
ues.
TER SET command with bits A7 and A9–A11 (128MB);
A7 and A9–A12 (256MB, 512MB); or A7 and A9–A13
(1GB) each set to zero, bit A8 set to one, and bits A0–A6
set to the desired values. Although not required by the
Micron device, JEDEC specifications recommend
when a LOAD MODE REGISTER command is issued to
reset the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
COMMAND
COMMAND
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
The normal operating mode is selected by issuing a
A DLL reset is initiated by issuing a MODE REGIS-
200-PIN DDR SDRAM SODIMM
DQS
DQS
CK#
CK#
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
CK
CK
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
T1
T1
©2004 Micron Technology, Inc. All rights reserved.
T2
NOP
NOP
T2
T2n
T2n
ADVANCE
DON’T CARE
T3
NOP
NOP
T3
T3n
T3n