CLA200 Zarlink Semiconductor, CLA200 Datasheet - Page 2

• Manufacturer Part Number: CLA200
• Description: CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

CLA200 Series
2
ARRAY ARCHITECTURE
The CLA200 Series gate array family is based on a sea of
gates array architecture. The arrays consist of a core of
transistors, overlaid with a core power supply grid, ringed by
three concentric pairs of VDD and GND supply rail. The
OPVDD rail can be split to form an extra VDD rail named split
supply VDD (SSVDD) to allow mixed voltages interfaces on
the same device. The outermost area of the die has pads for
I/O and power supplies.
Each array has a number of preferred pads designated for
power supply, This allows the use of a generic probe card to
reduce cost and allow rapid prototype turnaround.
Connections within the array are made using three or four
layers of metal. Each pad has one I/O location associated with
it.
CELL LIBRARIES
The CLA200 Series is supported by a comprehensive cell
library which is optimised for synthesis and includes basic
logic gates, oscillators and memories. In addition a range of
ready made system Macro functions such as a UART is also
available.
Advance Information
CORE ARCHITECTURE
The core area consists of a dense array of core cells. Each
core cell contains four transistors, two NMOS and two PMOS,
whose sizes have been optimised for high density and low
power. These are built from one structure consisting of a
shared central source/drain region with independently
available polysilicon gates. This core cell layout has been
designed to allow very efficient metal interconnections
including over-cell routing resulting in high utilisation. The core
architecture also allows highly efficient register file RAM to be
implemented.
Core Microcells
A wide range of core microcells are available including basic
logic cells, combinatorial logic, latches and D- Type Flip-Flops.
The basic logic cells, such as inverters, NAND and NOR gates
are available with a choice of drive strengths allowing
designers to make trade-offs between speed, power and
silicon area. A range of D-Type flip-flops is also available
including versions with multiplexers to facilitate Scan path
testing.