CLA200 Zarlink Semiconductor, CLA200 Datasheet - Page 8

• Manufacturer Part Number: CLA200
• Description: CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

CLA200 Series
CMOS and TTL Output Levels
Output Currents
Voltage Derating
Voltage derating is divided into two ranges, one for designs at 2.0V nominal and one for 3.3V nominal. The following figures
show how gate delay varies with supply voltage.
8
1.3
1.2
1.1
0.9
0.8
0.7
0.6
1
1.8
Derating for a 2.0V Supply (2 Volt normalised to 1)
All characteristics are over all process conditions from -40 to +85 C
Note: These figures apply for all Output Current Conditions shown below
CMOS
TTL
1.9
Device Voltage
1.8V < VDD < 2.2V
2.2V < VDD < 2.7V
2.7V < VDD < 3.3V
3.3V < VDD < 3.6V
Voltage Derating, 2.0V Nominal
2
Parameter
Voh
Voh
2.1
Vol
Vol
Voltage
2.2
Advance Information
0.8 VDD
0.8 VDD
1mA
1mA
2mA
2mA
2.3
I
Min
ol
x01
2.4
1mA
1mA
2mA
2mA
I
oh
2.5
Typ
3mA
4mA
2mA
2mA
I
ol
x03
Drive Strength
1.5mA
3mA
2mA
2mA
I
Derating for a 3.3V Supply (3.3 Volt normalised to 1)
1.4
1.3
1.2
1.1
0.9
0.8
oh
1
0.2 VDD
Max
0.4
10mA
12mA
6mA
8mA
I
ol
x06
Voltage Derating, 3.3V Nominal
Units
10mA
12mA
3mA
6mA
V
V
I
oh
Conditions
1.8V < VDD < 2.2V
3.0V < VDD < 3.6V
12mA
16mA
20mA
24mA
Voltage
I
ol
x12
12mA
20mA
24mA
6mA
I
oh