CLA200 Zarlink Semiconductor, CLA200 Datasheet - Page 5

• Manufacturer Part Number: CLA200
• Description: CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

Stage 1
Stage 2
Figure.2
Figure.1
Stage 1 output grid
Stage 2 output grid
Stage 3 output grid
Stage 3
Advance Information
Advanced Delay Modelling
Delay calculation includes the following features:
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Pin to Pin Delays
Delay models use times between individual input and output
pins for both rising and falling delays, as illustrated in figure 3
below.
Calculation uses individual pin to pin delays, e.g. A to F and B
to F, which improves simulation accuracy by modelling the
considerable variation in delay between different input pins.
For complex gates (e.g. AND-NOR gates or adders) the
variation is up to 40%. For simple NAND and NOR logic gates
the typical variation is 20%.
Non-linear Curve Fitting
For fast input edges (0.5ns) delay time increases linearly with
the output load, whereas for high output loads delay increases
linearly with edge speed. Delays for slow input edges and light
input loads do not follow the linear model, so a simple linear
model cannot represent delays accurately. A more complex
equation, which includes interaction between edge and load
factors, is used to model delays.
Thermal Management
The increase in speed and density available through
advanced CMOS processes results in a corresponding
increase in power dissipation. Designs can now have more
than half a million used gates and chip power consumption is
an important issue.
The CLA200 series offers the following:
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Edge speed modelling
Pin to pin timings
Non-linear delay modelling
Accurate delay derating
Conditional delay modelling
Lower power CMOS for improved thermal management
Software constructed power grids for efficient power
distribution
Copper lead frame QFPs for lower thermal resistance
High pinout power packages available
A
B
C
Figure.3
CLA200 Series
F
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