CLA200 Zarlink Semiconductor, CLA200 Datasheet - Page 3

• Manufacturer Part Number: CLA200
• Description: CMOS Gate Arrays
• Manufacturer: Zarlink Semiconductor

I/O Cells
The CLA200 series design libraries contain a wide variety of
Input, Output and Bi-directional cells, each of which is
available in a number of variants.
CLA200 series I/Os have the following features:
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The CLA200 has four separate VDD supply rails and two GND
rails, one VDD rail for the core, one for input buffers, and two
for output areas of the chip. The intermediate buffer supply rail
can be completely isolated for very low noise. This offers the
benefit of good noise immunity with multiple supply voltage
capability to suit the application. The mixed 2 and 3.3V I/O
capability can be used for power saving or interfacing with 2V
and 3.3V systems. 5V tolerant input and output cells are also
available to offer the advantages of a very low power core
whilst interfacing to 5V systems.
Electrostatic discharge (ESD) protection is built into the input
and output cells, and is specified to withstand at least 2kV
(human body model). The structure and process is also highly
resistant to latch-up and able to withstand forward bias
currents in excess of 200mA.
Cell library contains distinct and complete inputs, outputs
and bidirectionals to allow direct pad synthesis
Selectable I/O output speeds allow the designer to
maintain low noise and reduce the number of power
supply pins if output speed is not critical
Choice of Output drive strengths
Device I/O can run at a higher voltage than the core with
no static power consumption while still benefiting from a
low voltage, low power core
All input and output cells are non inverting
The input TTL and CMOS level detection circuits use low
noise power rails
I/O cells are optimised for 3.3V +/- 10% and are fully
functional down to 1.8V with derated current and speed
Inputs and bidirectionals are available with hold options.
The hold option maintains the last value (high or low) when
all drive to the pin is withdrawn.
All inputs have an optional internal pull-up or pull-down
resistor which are gated to enable IDDQ testing.
5V tolerant inputs and open drain outputs are available for
all devices
Mixed Voltage I/O Capability
Output currents up to 12mA @ 3.3V supported from a
single I/O cell. 24mA current drive available using two
output cells
Advance Information
SystemBuilder™
The SystemBuilder™ library contains a broad range of
macrofunctions designed to improve designers efficiency. All
of the SystemBuilder™ macrofunctions are supplied as
synthesizable RTL models for both VHDL and Verilog. In
addition each macrofunction is fully supported with synthesis
scripts, test-benches and full documentation.
The SystemBuilder™ library includes the following function :
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In addition to the above functional replacements for industry
standard devices the SystemBuilder™ library also contains a
range of clearly defined functions that are frequently required
for Systems Level integration (SLI) ASIC’s.
Further functions are continually being added. An up to date
list may be obtained from all Zarlink Semiconductor Sales and
Design Centers.
Standard Microprocessor Cores including 8048, 8051 &
8086
Standard Microprocessor peripherals including DMA
controllers, programmable interval timers, real time clock
& Programmable interrupt controllers.
Floppy Disc/Tape functions including controllers and data
separators
Standard Serial Communications controllers including
85C30, 16C450, 8251 & 8250
Bus interface cores including PCMCIA, Ethernet,
IEEE1284, USB and PCI
CLA200 Series
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